L64105 LSI Logic Corporation, L64105 Datasheet - Page 87

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.3
Read
Write
Event Mask
DTS Video
DTS Video
Interrupt
Event
Register 2 (0x002)
7
Begin Vertical Blank Interrupt
SCR Overflow Interrupt
SCR Compare Interrupt
Pack Data Ready Interrupt
Host Interface Registers
Event Mask
DTS Audio
DTS Audio
Interrupt
Event
6
Reserved
Reserved
The Video Interface module sets this bit and asserts
INTRn (if not masked) at the beginning of the vertical
blanking interval. This time is defined by the Vcode in the
Start of Active Video/End of Active Video (SAV/EAV)
timing codes programmed into the Video Interface.
This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
This bit is set and when the System Clock Reference
(SCR) counter
when read. INTRn is also asserted unless the host sets
the mask bit.
This bit is set when the System Clock Reference (SCR)
Compare mode is enabled and a match between the
value stored in the SCR Compare/Capture registers
(page
This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.
This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects the start of a pack. The
interrupt alerts the host that the pack header, system
header, and first packet pointer are in the channel buffer.
This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
5
4-13) and the current value of the SCR occurs.
Seq End
Seq End
Channel
Interrupt
Channel
Code in
Code in
Video
Video
Mask
4
(page
Reserved
Reserved
3
4-13) overflows. This bit is cleared
Data Ready
Data Ready
Video PES
Video PES
Interrupt
Mask
2
Data Ready
Data Ready
Audio PES
Audio PES
Interrupt
Mask
1
Pack Data
Pack Data
Interrupt
Ready
Ready
Mask
0
4-5
5
6
7
0