L64105 LSI Logic Corporation, L64105 Datasheet - Page 16

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L64105

Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
Tables
xvi
11.9
11.10 Synchronous AVALIDn/VVALIDn Signals Timing
11.11 Reset Timing
11.12 Video Interface Timing
11.13 Serial PCM Data Out Timing
11.14 A_ACLK Timing
11.15 PREQn Timing
11.16 160-Pin Package Pinout
11.17 160-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2)
A.1
A.2
A.3
A.4
A.5
A.6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
4.3
4.4
5.1
5.2
5.3
6.1
6.2
6.3
6.4
Contents
Asynchronous Channel Write Timing
MPEG Macroblock Structure
Typical Sequence of Pictures in Display Order
Typical Sequence of Pictures in Bitstream Order
Audio Encoding Process (Simplified)
ISO System Stream
MPEG Audio Packet Structure
L64105 Register Groupings
Host Interface Registers
Video Decoder Registers
Memory Interface Registers
Microcontroller Registers
Video Interface Registers
Audio Decoder Registers
RAM Test Registers
Display Mode Selection Table
MPEG Bitrate Index Table
Audio Decoder Modes
ACLK Divider Select [3:0] Code Definitions
Host Interface Signals
SCR Compare/Capture Mode Bits
DMA Mode Bits
Levels of Hierarchy in MPEG-1 and MPEG-2
System Syntax
Video Stream Select Enable Bits
Audio Stream Select Enable Bits
Pack Header Enable Bits
11-14
11-15
11-15
11-16
11-17
11-17
11-18
11-25
11-26
3-14
3-17
3-20
3-24
3-27
4-64
4-73
4-81
4-86
5-14
6-10
6-11
A-3
A-6
A-6
A-8
A-9
A-9
3-1
3-2
3-7
5-2
5-6
6-2
6-9

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