L64105 LSI Logic Corporation, L64105 Datasheet - Page 331

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 9.19 Pulldown Operation Timing
Normal Sequence
9.13 Video Output Format and Timing
3:2 Pulldown
Host Repeat
Odd/Even
Field First
First Field
Host Top
E
Output timing of video and control signals is shown in
Video Interface outputs 8-bit video compatible with 4:2:2 ITU-R BT.601
format. The video is synchronous with the 27-MHz SYSCLK. During the
blanking interval, luma data is set to 16 (black level), and Cb and Cr are
both set to 128 (zero level). Output data is clipped to ITU-R BT.601 levels
where luma has a range of 16 to 235 and chroma has a range of 16
to 240, giving exception to the SAV/EAV timing codes. To insert the ITU-
R BT.656 SAV/EAV timing codes into the pixel data stream, the host must
set the ITU-R BT.656 Mode bit in Register 284
may optionally set the CrCb 2’s Complement bit in Register 284 to
change the chroma outputs to 2’s complement format with the center
value equal to 0 instead of 128.
The Video Interface also outputs an active high BLANK signal that is
based upon the programmed SAV/EAV values for h-blank and v-blank.
When high, the CREF output indicates that the current byte on the output
data bus is Cb data.
Video Output Format and Timing
T0
T0
O
B0
B0
E
T1
T0
O
B1
B1
E
T2
T1
O
B2
B2
E
(page
4-68). The host
Figure
T3
T2
O
9.20. The
B3
B2
E
9-39