L64105 LSI Logic Corporation, L64105 Datasheet - Page 443

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

SDQM signal
SDRAM 1-5,
description
accessing 1-3,
address bus 2-7,
addresses, incrementing
block moves 4-40, 4-43, 5-10, 5-14,
chip select
clock 2-8,
column address select
configurations
control pin
data bus 2-7,
data transfers 4-39, 4-41, 5-10,
devices
elementary stream read/writes 6-13,
external write pointers
frame stores 1-5,
host accesses
host reads 4-41,
host writes 4-41,
interface on-chip display controller
internal state
MPEG-1 system channel buffer addresses
off-chip writes
OSD addresses
overflow/underflow interrupts
PCB layout connections
reads 4-46, 4-47, 7-2,
reads cycle timing diagram
recommended size 1-3,
reducing bandwidth demand
refresh rate 4-40,
refresh timing
row address select
source addresses 4-42, 4-46,
space allocation
space limited
target addresses 4-42, 4-46,
timing requirements
total memory space
transfer byte ordering
transfer done interrupt bit
caution
complete
flowchart
external
starting addresses
timing cycles
incrementing
nonincrementing
incrementing
overriding
7-3
B-8
2-11
2-7
2-7
5-18
2-7
2-7
8-30
5-19
4-3
4-44
9-19
9-15
7-1
7-5
7-2
6-9
5-10
1-5
9-26
5-15
7-6
5-16
7-4
5-10
5-10
7-1
7-11
7-5
2-7
7-3
5-15
1-5
Index
4-40
to
4-42
to
9-2
6-27
2-7
2-7
to
2-7
5-15
5-13
5-13
4-3
7-5
11-7
4-54
5-12
4-7
5-11
5-14
8-30
5-18
6-14
6-18
SDRAM read pointers
SDRAM-NEC 16 Mbit
select pin (host)
selection modes
self-clocking interface
sequence end code detect interrupt bit
sequence end code in video channel interrupt bit
sequence extensions 8-6,
sequence headers 8-4,
sequencing ignore
serial audio signal
serial data bit clock 2-10, 10-6,
serial frames
serial interfaces
serial PCM data out timing
serial streams
set top box
setting up rip forward/display override
SI
SIF
SIF resolution 9-16, 9-17,
SIF-format MPEG-2 images
signal
B-7
underflow interrupts
video frame stores
write enable
write timing cycles
writes 4-46, 4-47, 7-2,
writes cycle timing diagram
usage overview
quant matrix values
search enable
unencoded data
See also streams
command diagram
A[8:0]
A_ACLK
ACLK_32
ACLK_48
ACLK_441
AREQn
ASDATA
ASn
AUDIO_SYNC
AVALIDn
BCLK
BLANK
BUSMODE
CD_ACLK
CD_ASDATA
CD_BCLK
CD_LRCLK
B-7
starting addresses
2-3
2-10
2-3
2-8
2-5
1-1
2-10
2-9
2-6
10-27
2-10
2-10
2-9
2-9
1-2
2-10
2-3
2-9
2-8
10-29
2-3
4-81
2-9
8-43
2-10
2-9
4-55
8-46
2-9
10-29
7-5
7-4
7-9
6-27
8-42
4-7
A-5
8-14
4-42
9-23
9-18
8-7
11-17
9-18
11-8
10-33
4-3
IX-27
4-6