L64105 LSI Logic Corporation, L64105 Datasheet - Page 426

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

digital data streams
digital equipment
digital overwrite category
digital transmission 8-bit timing
digitized audio stream
discrete cosine transform (DCT)
display areas
display controller 4-65, 9-2,
display controller interface on-chip
display extension
display frames
display freeze 7-11,
display mode bits
display modes 8-33, 8-41,
display override
IX-10
background selection
end column 9-11,
end row
example
getting locations
large
multiple 9-28,
positioning vertically
start column 9-11,
start row
storage layout
vertically filtered
blank output 2-8,
blanking intervals
display mode enable
even/odd field indicator and
horizontal pan and scan 4-66,
initializing display parameters
interrupt generation
interrupts
letterbox filtering
main region
offset counters
output
override registers
postprocessing filters
still image display 9-13,
vertical pan and scan 4-66,
freezing 8-37,
usage overview
enabling
enhanced resolution
override bit
selection table 4-64,
chroma frame store start address bits
luma frame store start address bits
formats
SDRAM addresses
9-19
9-30
9-27
9-6
4-63
9-26
9-40
9-5
9-28
4-59
4-70
9-30
10-29
8-40
to
8-7
9-24
4-63
9-6
9-16
to
9-6
A-8
9-6
9-36
9-16
9-12
9-2
9-7
9-14
9-27
9-27
A-8
9-29
9-7
9-12
9-18
9-17
4-63
Index
9-13
9-20
4-88
to
9-26
9-16
9-15
9-5
9-37
9-35
9-12
2-9
to
A-3
9-4
9-33
9-19
8-30
4-68
4-68
display override mode 8-41,
display parameters
display rates 8-24,
display start command bit
display start override
DMA
DMA bandwidth
DMA controller
DMA mode bits 4-39,
DMA SDRAM read data bits
DMA SDRAM read/write flowchart
DMA SDRAM source address bits
DMA SDRAM target address bits
DMA SDRAM write data bits
DMA transfer byte ordering little/big endian bit
DRAM
DREQn signal
DSn signal
DTACKn signal
external OSD controller
block moves 4-40,
block moves flowchart
data transfer request
data transfers 1-3,
dual-address
external data transfers
external request
idle state
reads 5-15,
registers
terminal count
video data transfers
writes 5-16,
current state
description
synchronous transfers and
usage overview
description
description
B-2
host directed
source addresses
target addresses
audio sync error detection
current state
hardware sync controls and
host interface
maximum transfer rate
status 4-10,
transfer count 5-15,
maximum transfer rate
starting addresses
maximum transfer rate
starting addresses
B-2
2-3
4-38
4-39
2-5
2-3
2-4
2-5
5-17
5-17
2-4
5-18
4-39
5-15
5-14
4-38
9-30
9-4
5-14
4-39
5-18
2-5
5-14
4-59
5-14
5-14
5-12
4-46
2-5
4-46
4-46
4-46
to
5-19
4-72
5-16
9-32
9-15
5-18
4-47
4-47
6-3
2-5
2-6
6-7
10-5
4-46
5-17
4-46
2-10
4-41