L64105 LSI Logic Corporation, L64105 Datasheet - Page 362

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.9.1 Biphase Mark Coding
Figure 10.13 IEC958 Biphase Mark Representation
Biphase Mark
10.9.2 IEC958 Syntax
10-30
Data Clock
Encoded
Output
BCLK
Data
in
either the output of the interface or the SPDIF_IN when the host selects
the S/P DIF Bypass Mode.
To minimize the DC component on the transmission line, facilitate clock
recovery from the bitstream, and make the interface insensitive to the
polarity of connection, the bitstream is encoded in biphase marks.
Refer to
Divider (see
biphase marks. The S/P DIF BCLK rate is sample frequency x sample
resolution x 2 channels x 2 biphase marks/bit.
Each bit is represented by a symbol with two consecutive binary states,
1 bits by two opposite states and 0 bits by two equal states. The first
state of a symbol is always different from the second state of the
previous symbol. This forces the data stream to transition at least once
for every bit.
The IEC958 stream is organized into blocks of 192 frames with each
frame containing two subframes, one for each audio channel as shown
in
sampling frequency when the input audio source is sampled at 32, 44.1,
or 48 kHz. When the input data is 96-kHz Linear PCM samples, the
samples are decimated down to 48 kHz in the decoder for the S/P DIF
output.
Audio Decoder Module
1
Section 10.9.2, “IEC958 Syntax.”
Figure
Figure
10.14. The frame transmission rate is equal to the source
0
Section 10.10, “Clock
10.13. BCLK, derived from an ACLK input in the Clock
0
1
Divider”), divides each data bit into
The output demultiplexer selects
1
0