L64105 LSI Logic Corporation, L64105 Datasheet - Page 265

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

The status changes from empty to data ready as soon as the first byte
is written into the FIFO. Once overrun (0b11) occurs, the status remains
at overrun until the host reads the register, and then changes to full until
a byte is written in or read out. The Postparser must keep writing user
data bytes into the FIFO as it encounters them in the bitstream. Bytes
which overflow from the FIFO are lost. The host is not interrupted on
overrun so it must watch the status bits and empty the FIFO in a timely
manner.
Once the Postparser is past the first slice start code of the picture, the
remaining data in the picture belongs to the slice, macroblock, and block
layers. Usually, all the auxiliary/user data pertaining to the current picture
has already been written to the FIFOs when the first slice start code in
the picture is encountered. Also at this point, the Video Decoder stalls to
synchronize with the display process, giving the host ample time to read
the FIFOs.
The three host options are then:
1. mask both interrupts and routinely read the FIFO status.
2. mask the First Slice Start Code Detect Interrupt and read the FIFO
3. mask the Aux/User Data Ready Interrupt and read the FIFO contents
When the first data byte is written to the FIFO, it is placed in the User
Data FIFO Output register. At the same time, the Postparser writes the
layer ID of the data byte into the User Data Layer ID field of
(0x41)
the data. As soon as the data byte is read, the two registers are updated
if another unread byte is available in the FIFO.
Postparser Operation
status when INTRn is asserted because of an Aux/User Data Ready
Interrupt.
when the First Slice Start Code Detect Interrupt occurs.
Note:
(see
Table
It is important for the host to respond to INTRn and read
the interrupt registers. The interrupt bits are cleared when
read. If one FIFO sets the data ready interrupt bit and the
bit is not read, the other FIFO cannot generate an interrupt.
8.17). The host should read the ID first and then read
Register 65
8-23