L64105 LSI Logic Corporation, L64105 Datasheet - Page 224
L64105
Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
1.L64105.pdf
(454 pages)
- Current page: 224 of 454
- Download datasheet (5Mb)
6.4.1 Buffer Reset
6-28
Each of the buffers can be reset on an individual basis, i.e., without
affecting the other buffers. Resetting a buffer returns its read and write
pointers to the buffer start address. A buffer is reset when the host sets
the corresponding bit in Register 68
register is set, all defined buffers are reset when a packet sync error is
detected.
The Channel Buffer Controller provides a compare function for extracting
actual Decode Time Stamp (DTS) values, i.e., the actual time when a
picture or audio frame has started decoding. The host registers
associated with this function are listed in
Table 6.13
When the Enable Video Read Compare DTS bit is set, the value in the
Video ES Channel Buffer Compare DTS Address registers is constantly
compared with the current value of the video channel read pointer. As
soon as a match is detected, a signal is generated that triggers a state
machine. When the state machine detects a Picture Start Code, the
INTRn output to the host is asserted, if not masked, and the DTS Video
Event Interrupt bit in Register 2
In an actual situation, the host, when alerted, would read the packet
header and the start address of a packet payload from the Audio PES
Header/System Channel Buffer and write that address to the Video ES
Channel Buffer Compare DTS registers. At the first Picture Start Code
after the read pointer for the Audio PES Header/System Channel Buffer
reached the compare address, the host would be alerted to the start of
decoding for that picture. The host would then read the value of the SCR
counter as the DTS.
Channel Interface
Function
Enable Video Read Compare DTS
Enable Audio Read Compare DTS
Video ES Channel Buffer Compare DTS Address
Audio ES Channel Buffer Compare DTS Address
Compare DTS Register Bits and Fields
(page
(page
4-6) is set.
Table
4-20). When bit 0 in the
6.13.
Registers
108–110
111–113
69
69
Page Ref.
4-21
4-21
4-28
4-29
Related parts for L64105
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Satellite Decoder Technical Manual 5/97
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Receiver
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner/receiver Chipset
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Smatv Qam Encoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
DVB Qam Modulator
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Dvb-t Cofdm Demodulator Technical Manual 2/00
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
16-Bit HCMOS Multiplier / Accumulators
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Transport with Embedded CPU and Control
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
32-Bit HCMOS IEEE Floating-Point Processor
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Variable-Length Video Shift Registers
Manufacturer:
LSI Logic Corporation