L64105 LSI Logic Corporation, L64105 Datasheet - Page 149

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.100 Register 283 (0x11B)
Figure 4.101 Register 284 (0x11C)
Reserved
Reserved
7
7
VSYNC Input
Type
6
6
Override Picture Width [6:0]
Reserved
ITU-R BT.656 Mode
Sync Active Low
Reserved
Pixel State Reset Value [1:0]
Video Interface Registers
Complement
CrCb 2’s
5
Pixel State Reset Value [1:0]
This field contains the picture width of the override frame
store in 8-pixel increments. In other words, this field
should be programmed with picture width in pixels
This field is used only when the Display Override Mode
bits (Register 265, bits 4 and 5,
0b01 or 0b10.
Clear this bit when writing to this register.
When this bit is set, the L64105 sends out a 4-word code
for the start and end of active video at blanking time.
When this bit is set, the L64105 expects active low
Horizontal and Vertical Sync inputs. If the bit is cleared,
the chip expects active high sync inputs. The host should
set this bit to match the sense of the sync inputs from the
NTSC/PAL encoder.
Clear this bit when writing to this register.
The pixel state machine is initialized by the Horizontal
Sync pulse. The initial state of this field is programmed
by the host. This allows the host to adjust the pixel state
timing such that the main region starts on the Cb state.
This state machine follows this sequence; Cb, Y, Cr, Ys,
Cb. The Pixel State Reset Values are calculated using
the following formula:
Pixel State Reset Value = (Main Start Column + 2) mod 4.
4
Override Picture Width [6:0]
3
Reserved
2
page
Sync Active
Low
4-59) are set to
1
ITU-R BT.656
R/W [6:0]
R/W [4:3]
Mode
R/W 0
R/W 1
0
0
4-67
8.
7
2