L64105 LSI Logic Corporation, L64105 Datasheet - Page 143

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.90
Figure 4.91
Reg. 270
Reg. 271
Reg. 272
Reg. 273
Reserved
MSB
MSB
LSB
LSB
7
Filter Enable
Decimation
Horizontal
Registers 270–273 (0x10E–0x111) OSD Odd/Even Field Pointers [15:0]
Register 274 (0x112)
7
6
The host can program the addresses of the OSD Odd/Even Field
Pointers into these registers. The addresses are in 64-byte resolution.
OSD Mix Weight[3:0]
OSD Chroma Filter Enable
Reserved
Horizontal Decimation Filter Enable
Reserved
Video Interface Registers
Reserved
5
OSD Chroma
This register is used by the host to specify the OSD mix
weight in external OSD Mode only. When using internal
OSD, the mix weight is specified in the OSD header
stored in SDRAM. When programmed to zero, the mixed
video output is 100% video and 0% OSD. When
programmed to 0xF, the mixed video output is 1/16 video
and 15/16 OSD.
When this bit is set, the chroma enhancement filter is
enabled for OSD overlay images.
Clear this bit when writing to this register.
When this bit is set, the 2:1 horizontal decimation filter is
enabled.
Clear this bit when writing to this register.
Filter Enable
OSD Even Field Pointer [15:8]
OSD Odd Field Pointer [15:8]
OSD Even Field Pointer [7:0]
4
OSD Odd Field Pointer [7:0]
R/W
R/W
R/W
R/W
3
OSD Mix Weight[3:0]
R/W [3:0]
R/W 4
R/W 6
0
0
4-61
5
7