L64105 LSI Logic Corporation, L64105 Datasheet - Page 204

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

6.2.4 Channel Bypass Mode
6.2.5 Channel Pause
6-8
The internal request (int_req) signal is generated by the channel input
FIFO controller on the L64105 and indicates available room in the on-
chip buffers and the SDRAM channel buffers. The internal request signal
is always registered by the L64105 SYSCLK. Normally, A/VREQn signals
are asserted even when the channel is stopped to prevent upstream
device overflow. The host can set the Channel Pause bit to block the
int_req. If not, the SYSCLK-registered int_req is routed through the
output multiplexer to the appropriate A/VREQn pin.
When the Channel Request Mode bit is set by the host, the Sync input
to the multiplexer is selected. As was shown in
can be inverted or not through the exclusive OR. In either case, the
internal request is registered by a rising and falling internal DCK to avoid
metastability. The external AREQn/VREQn signals always change at the
falling edge of the Internal DCK. Refer to
When the Channel Bypass Enable bit in Register 5
the L64105 reads audio and video data in from the host through the A/V
Channel Bypass Data registers
data channel input port and the AVALIDn and VVALIDn input signals are
ignored. The AREQn and VREQn output signals still function normally
and can be used by the host as DMA control handshake signals. When
either is asserted, the internal microcontroller watches the corresponding
Channel Bypass Data register for activity. The Channel Bypass Data
registers can accept one additional byte after the AREQn or VREQn
signals are deasserted.
When the Channel Pause bit in Register 5
A/VREQn outputs of the L64105 are held deasserted. This does not stop
the channel processing inside the L64105. This function is intended to
be used to force a pause of either transport decoder devices or channel
decoder devices that respect the AREQn and VREQn signals. While
paused, the host can change stream IDs at known boundaries, but it
cannot change any of the address ranges or the setup of the Preparser
read and write pointers.
Channel Interface
(page
4-16). In this mode, the parallel
Chapter 11
(page
Figure
4-10) is set, the
(page
6.3, the DCK input
for exact timing.
4-10) is set,