L64105 LSI Logic Corporation, L64105 Datasheet - Page 361

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.9 S/P DIF Interface
The ASDATA bits are clocked out on every BLCK falling edge. The
A_ACLK is the DAC clock and is at 256 or 384 times the sample
frequency depending on the DAC used.
LRCLK specifies which PCM channel, left or right is currently being
transferred. The Invert LRCLK bit in Register 363
the LRCLK state channel assignment. The bit defaults to the clear state
at reset and power on. This sets LRCLK high for left channel sample
outputs and low for right channel outputs. The host can invert this sense
(high for right; low for left) by setting the Invert LRCLK bit.
The DAC Interface also uses a special, soft-muting scheme to avoid a
click on the speakers when the output is turned off. The host can set the
Mute on Error bit in Register 358
audio output when certain errors occur in the bitstream or the decoder.
The host can also mute the audio outputs by setting the User Mute Bit
in Register 358. An Audio Decoder Soft Mute Status bit is available in
Register 354
When the host programs the Audio Decoder Mode Select bits in Register
357 to 0b110 to select the CD Bypass Mode, the output demultiplexer
substitutes the CD_ASDATA, CD_BCLK, CD_LRCLK, and CD_ACLK for
the normal outputs of the DAC Interface.
The S/P DIF (IEC958) Interface is a serial, unidirectional, self-clocking
interface for the interconnection of digital equipment for consumer and
professional applications. The L64105 supports the consumer output
mode only, which carries stereophonic digital programs with a resolution
of up to 16 bits per sample. Twenty and 24-bit samples are clipped by
dropping the least significant 4 or 8 bits.
The demultiplexer at the interface input is controlled by the Audio
Decoder Mode Select bits in Register 357
output of either of the two decoders or the output of the formatter. The
interface serializes the selected samples and formats them as described
S/P DIF Interface
Note:
Some DACs have an on-chip Phase-Locked Loop (PLL) to
derive their operating clock from the incoming bit clock. The
A_ACLK output of the L64105 is not used in this case.
(page
4-78) for the host to read.
(page
4-82) to force a soft-mute of the
(page
(page
4-81) to select the
4-84) determines
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