L64105 LSI Logic Corporation, L64105 Datasheet - Page 337

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Each audio frame in MPEG and Linear PCM streams starts with a sync
word and contains a fixed number of bytes. Once instructed to start, the
audio decoder looks for the first sync word and starts to decode
immediately after detecting it. However, the decoder does not go into “in
sync” state until it also detects the sync word in the following frame. Once
synchronized, the decoder loses synchronization only when it fails to
locate the sync word where it expects it to be in the next frame. When
this occurs, the decoder continues searching and sets the Audio Sync
Error Interrupt bit in Register 4
(page
4-8). If this bit is not masked,
INTRn is asserted to the host. When the decoder successfully finds three
consecutive sync words, it sets the Audio Sync Recovery Interrupt bit
and asserts INTRn to the host. Also, each time a sync word is detected,
the Audio Sync Code Detect Interrupt bit in Register 1
(page
4-3) is set
and INTRn is asserted.
The decoders also detect CRC errors (corrupted audio data) and illegal
bit errors (invalid bitstream parameters). When either is encountered, the
decoders set the Audio CRC or Illegal Bit Error Interrupt bit in Register
4, reset their internal counters and state machines, and start searching
for the next sync word.
If the host sets the Mute on Error bit in Register 358
(page
4-82), the
audio output is muted during any of the previous errors to avoid sending
out bad samples (noise) to the speaker(s). When the Audio Decoder
Module is stopped, the decoders stay in the idle state and the read and
write pointers of the Audio ES Channel Buffer are reset.
The formatter takes the encoded audio frames from the Audio ES
Channel Buffer, adds a preamble to them, and pads them out into S/P
DIF bursts. The formatter can run simultaneously with the decoder and
detect out-of-sync conditions with the decoder. The formatter can then
insert pause bursts, as necessary, to resynchronize or the host can
substitute zeros for the pause bursts.
The 16-, 20-, or 24-bit decoded audio samples that are input to the DAC
interface are converted to 32-bit serial output (ASDATA). This format is
obtained by sign extension of the input data.
The S/P DIF interface only supports 16-bit input data samples. The input
to the S/P DIF interface comes either from the decoders or from the
audio formatter. It produces a fixed-length, 32-bit packet per input sample
and then represents each bit with two consecutive binary states (biphase
mark) as a clock self-recovery technique.
Audio Decoder Overview
10-5