L64105 LSI Logic Corporation, L64105 Datasheet - Page 25

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 1.2
(27 MHz)
SYSCLK
Address
Control
Status
Buses
Data
and
and
DCK (£ 9 MHz)
L64105 Decoder
CH_DATA[7:0]
L64105 Decoder Block Diagram
Interface
Host
The read and write FIFOs are used to give the host access to the
external SDRAM. The read/write paths are still through registers. The
interface supports direct read/write, DMA transfers using an external
DMA controller, and block moves within SDRAM. The byte enable logic
converts host byte writes to 8-byte words for the write FIFO and 64-bit
internal bus and vice versa. The byte enable logic also performs byte
switching for little endian hosts.
The Channel Interface accepts byte-wide MPEG streams and a clock.
The interface synchronizes to and preparses the incoming stream by
stripping system headers and storing them in a dedicated buffer area in
SDRAM. The interface also separates the audio and video streams and
stores them in dedicated buffer areas in SDRAM. A buffer controller
maintains the read and write pointers for the dedicated buffers.
The Memory Interface includes byte enable logic and an address
converter. The recommended SDRAM is 16 bits wide, so the byte enable
logic performs the conversion between the SDRAM bus and the 8-byte
wide internal bus of the L64105. The host and internal microcontroller of
L64105 Overview
SDRAM Buffers and
Frame Stores
Interface
Memory
Interface
Channel
Microcontroller
64-bit
Address Bus
Decoder
Video
Data Bus
Interface
Decoder
Video
Audio
Video to
NTSC/PAL
Encoder
I/O
Control
Audio
and
Clocks
to DAC
Oversampling
Clock In
S/P DIF
Out
1-3