L64105 LSI Logic Corporation, L64105 Datasheet - Page 203

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

6.2.3 Synchronous A/VREQn Outputs
Figure 6.5
SYSCLK
DCK In
int_req
Pulldown
Resistor
Invert Channel Clock Bit
L64105 A/VREQn Circuits
Channel Pause Bit
Register 5
Register 5
fsm
2. It is recommended that the AVALIDn and VVALIDn outputs are
3. The minimum period of DCK must be
4. The system must respect the function of the AREQn/VREQn signals.
If the upstream device requires that the DREQn outputs of the L64105
be synchronized to DCK, setting the Channel Request Mode bit
configures the L64105 appropriately. The A/VREQn circuits for one
request signal in the decoder are shown in
Interface Signals Operation
registered on the rising edge of DCK (if DCK is in normal mode, i.e.,
not inverted mode.)
37 ns). This allows the internal synchronizing logic time to
resynchronize, and allows the input channel FIFO time to assert and
deassert the AREQn/VREQn signals and prevent overflow
conditions.
The timing restriction above will allow enough space within the input
channel FIFO to allow an external synchronizer on the AREQn/
VREQn signals. This allows writing data beyond AREQn/VREQn
rising edge by 1 byte.
del4
Internal DCK
Figure
3 Tc (Tc = 1/27 MHz =
Async
Sync
Channel Request
Register 5
Mode Bit
6.5.
A/VREQn
6-7