CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet
CS8900-CQ3
Related parts for CS8900-CQ3
CS8900-CQ3 Summary of contents
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... Bus A Logic DS271PP3 DESCRIPTION The CS8900A is a low-cost Ethernet LAN Controller op- timized for Industry Standard Architecture (ISA) Personal Computers. Its highly-integrated design elimi- nates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA-Bus interface with 24 mA Drivers ...
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... Checking EEPROM for presence of Reset Configuration Block ...................................... 21 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block ...................................... 22 3.4.4 Groups of Configuration Data .................................................................................................... 22 3.4.4.1 Group Header................................................................................................................... 23 3.4.5 Reset Configuration Block Checksum ....................................................................................... 23 3.4.6 EEPROM Example .................................................................................................................... 23 3.4.7 EEPROM Read-out ................................................................................................................... 23 2 Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATA SHEET CS8900A DS271PP3 ...
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... Programming the EEPROM ................................................................................................................ 24 3.5.1 EEPROM Commands................................................................................................................ 24 3.5.2 EEPROM Command Execution................................................................................................. 24 3.5.3 Enabling Access to the EEPROM ............................................................................................. 25 3.5.4 Writing and Erasing the EEPROM............................................................................................. 25 3.6 Boot PROM Operation ........................................................................................................................ 25 3.6.1 Accessing the Boot PROM ........................................................................................................ 25 3.6.2 Configuring the CS8900A for Boot PROM Operation................................................................ 25 3.7 Low-Power Modes .............................................................................................................................. 26 3.7.1 Hardware Standby ..................................................................................................................... 26 3.7.2 Hardware Suspend.................................................................................................................... 26 3.7.3 Software Suspend ..................................................................................................................... 27 3.8 LED Outputs........................................................................................................................................ 28 3.8.0.1 LANLED ........................................................................................................................... 28 3 ...
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... Status and Control Bit Definitions .............................................................................................. 47 4.4.3.1 Act-Once Bits ................................................................................................................... 48 4.4.3.2 Temporal Bits ................................................................................................................... 48 4.4.3.3 Interrupt Enable Bits and Events...................................................................................... 48 4.4.3.4 Accept Bits ....................................................................................................................... 48 4.4.4 Status and Control Register Summary ...................................................................................... 49 4.4.5 Register 0: Interrupt Status Queue .......................................................................................... 52 4.4.6 Register 3: Receiver Configuration .......................................................................................... 53 4.4.7 Register 4: Receiver Event ...................................................................................................... 54 4 Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATA SHEET CS8900A DS271PP3 ...
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... PacketPage Pointer Port ......................................................................................................... 76 4.10.6 PacketPage Data Ports 0 and 1 .............................................................................................. 77 4.10.7 I/O Mode Operation ................................................................................................................. 77 4.10.8 Basic I/O Mode Transmit ......................................................................................................... 77 4.10.9 Basic I/O Mode Receive .......................................................................................................... 77 4.10.10 Accessing Internal Registers ................................................................................................. 78 4.10.11 Polling the CS8900A in I/O Mode.......................................................................................... 78 5.0 OPERATION ............................................................................................................................................. 79 5.1 Managing Interrupts and Servicing the Interrupt Status Queue .......................................................... 79 5.2 Basic Receive Operation..................................................................................................................... 79 5.2.0.1 Overview .......................................................................................................................... 79 5.2.1 Terminology: Packet, Frame, and Transfer ............................................................................... 81 5 ...
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... Configuring the Destination Address Filter ................................................................................ 88 5.3.2 Hash Filter ................................................................................................................................. 89 5.3.2.1 Hash Filter Operation ....................................................................................................... 89 5.3.3 Broadcast Frame Hashing Exception ........................................................................................ 89 5.4 Receive DMA ...................................................................................................................................... 90 5.4.1 Overview .................................................................................................................................... 90 5.4.2 Configuring the CS8900A for DMA Operation ........................................................................... 90 5.4.3 DMA Receive Buffer Size .......................................................................................................... 90 5.4.4 Receive-DMA-Only Operation ................................................................................................... 91 5.4.5 Committing Buffer Space to a DMAed Frame............................................................................ 92 5.4.6 DMA Buffer Organization ........................................................................................................... 92 5.4.7 RxDMAFrame Bit ....................................................................................................................... 92 5.4.8 Receive DMA Example Without Wrap-Around .......................................................................... 92 5 ...
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... WIRING........................................................................................................................... 120 7.6 AUI WIRING ................................................................................................................................... 121 7.7 QUARTZ CRYSTAL REQUIREMENTS............................................................................................ 121 8.0 PHYSICAL DIMENSIONS....................................................................................................................... 122 9.0 GLOSSARY OF TERMS......................................................................................................................... 123 9.1 Acronyms .......................................................................................................................................... 123 9.2 Definitions ......................................................................................................................................... 124 9.3 Acronyms Specific to the CS8900A .................................................................................................. 125 9.4 Terms Specific to the CS8900A ........................................................................................................ 125 9.5 Suffixes Specific to the CS8900A. .................................................................................................... 126 DS271PP3 CIRRUS LOGIC PRODUCT DATA SHEET 7 ...
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... AUI. 1.1.1 Direct ISA-Bus Interface Included in the CS8900A is a direct ISA-bus inter- face with full 24 mA drive capability. Its configu- ration options include a choice of four interrupts and three DMA channels (one of each selected dur- ing initialization) ...
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... The 10BASE-T transmitter and receiver im- pedance can be adjusted to support 100, 120, or 150 Ohm twisted pair cables. • An external Latchable-Address-bus decode cir- cuit can be added to operate the CS8900A in Upper-Memory space. adapter cards • On-chip LED ports can be used for either op- tional LEDs programmable outputs ...
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... The serial EEPROM port, used for configura- tion and initialization, eliminates the need for expensive switches and jumpers. • The CS8900A is designed to be used layer circuit board instead of a more expensive multilayer board. • The 8900A-based solution offers the smallest footprint available, saving valuable printed cir- cuit board area ...
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... DMACK1 11 DRQ7 DMARQ2 12 DACK7 DMACK2 15 SA[0:14] 8 SD[0:7] DS271PP3 SLEEP TEST RES 92 RXD- 91 RXD+ 24.3 88 TXD- 87 TXD+ 24.3 CS8900A 84 DO- 83 DO+ 82 CI- 81 CI+ 80 DI- 79 DI+ 39 BSTATUS/HCI 680 100 LANLED 680 99 LINKLED 17 CSOUT Boot-PROM 27C256 PD[0:7] Figure 3. Typical Connection Diagram ...
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... CSOUT 17 SD15 18 SD14 19 SD13 20 SD12 21 DVDD2 22 DVSS2 23 SD11 24 SD10 25 12 Crystal LAN™ ISA Ethernet Controller CS8900A 100-pin TQFP (Q) Top View CIRRUS LOGIC PRODUCT DATA SHEET CS8900A 75 RESET 74 SD7 73 SD6 72 SD5 71 SD4 70 DVSS4 69 DVDD4 68 SD3 67 SD2 66 SD1 65 SD0 IOCHRDY 64 63 AEN ...
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... I/O register onto the System Data Bus. IOR is ignored if REFRESH is low. IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. ...
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... IOCHRDY - I/O Channel Ready, Open Drain Output PIN 64. When driven low, this open-drain, active-high output extends I/O Read and Memory Read cycles to the CS8900A. This output is functional when the IOCHRDYE bit in the Bus Control register (Register 17) is clear. This pin is always 3-Stated when the IOCHRDYE bit is set. ...
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... Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM. When TEST is low, this pin becomes the output for the Boundary Scan Test. CSOUT - Chip Select for External Boot PROM, PIN 17. Active-low output used to select an external Boot PROM when the CS8900A decodes a valid Boot PROM memory address. 10BASE-T Interface TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88 ...
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... When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the host may drive this pin low by setting the HCBO in the Self Control register. ...
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... Ethernet frame into the CS8900A’s buffer memory. The first phase be- gins with the host issuing a Transmit Command. This informs the CS8900A that a frame transmitted and tells the chip when to start trans- mission (i.e. after 5, 381, 1021 or all bytes have been transferred) and how the frame should be sent (i ...
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... The CS8900A interfaces directly to the host DMA controller to provide DMA transfers of receive frames from CS8900A memory to host memory. The CS8900A has three pairs of DMA pins that can be connected directly to the three 16-bit DMA channels of the ISA bus. Only one DMA channel is used at a time ...
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... Upon exit, there is a chip-wide reset (see Section 3.7 on page 26 for more information about SW Suspend). 3.3.2 Allowing Time for Reset Operation After a reset, the CS8900A goes through a self con- figuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for validity and configuration. Time required for the reset calibra- tion is typically 10 ms ...
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... DMA channel conflicts on the ISA bus at power- up time. 3.3.4 Initialization After each reset (except EEPROM Reset), the CS8900A checks the sense of the EEDataIn pin to see if an external EEPROM is present. If EEDI is high, an EEPROM is present and the CS8900A au- tomatically loads the configuration data stored in the EEPROM into its internal registers (see next section) ...
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... EEPROM words, and a checksum value. All of the words in Pin the Reset Configuration Block are read sequential- Chip Select ly by the CS8900A after each reset, starting with Clock the header and ending with the checksum. Each group of configuration data is used to program a Data In PacketPage register (or set of PacketPage registers in some cases) with an initial non-default value ...
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... FFFFh is a special code indicating that there are no more words in the EEPROM. Table 6. EEPROM Configuration Block Example CS8900A will not attempt to read configuration data from the EEPROM. 3.4.3.5 Determining Number of Bytes in the Reset Configuration Block The low byte of the Reset Configuration Block header is known as the link byte ...
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... EEPROM Read-out If the EEDI pin is asserted high at the end of reset, the CS8900A reads the first word of EEPROM data by: 1) Asserting EECS 2) Clocking out a Read-Register-00h command on EEDO (EESK provides a 1MHz serial clock signal) 3) Clocking the data in on EEDI ...
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... If EEDI is high, the EEPROM is a ’C56, ’CS56, ’C66, or ’CS66. 3.4.7.2 Loading Configuration Data The CS8900A reads in the first word from the EE- PROM to determine if configuration data is con- tained in the EEPROM. If configuration data is not stored in the EEPROM, the CS8900A terminates initialization from EEPROM and operates using its default configuration (See Table 3) ...
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... ISA bus. 3.6.2 Configuring the CS8900A for Boot PROM Operation Figure 6 shows how the CS8900A should be con- nected to the Boot PROM and ’245 driver. To con- figure the CS8900A’s internal registers for Boot PROM operation, the Boot PROM Base Address ...
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... LAN is not in use, and then automatically restore Ethernet operation once the cable is reconnected Standby mode, all analog and digital cir- A1 cuitry in the CS8900A is turned off, except for the . ISA . SD(0:7) 10BASE-T receiver which remains active to listen BUS ...
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... SWSuspend bit (Register 15, SelfCTL, bit 8). To exit SW Suspend, the host must write to the CS8900A’s assigned I/O space (the Write is only used to wake the CS8900A, the Write itself is ig- nored). Upon exit, the CS8900A performs a com- plete reset, and then goes through a normal initialization procedure ...
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... Output is low Table 9. LINKLED/HC0 Pin Operation 3.8.0.3 BSTATUS or HC1 BSTATUS or HC1 can be controlled by either the CS8900A or the host. When controlled by the CS8900A, BSTATUS is low whenever the host reads the RxEvent register (PacketPage base + 0124h), signaling the transfer of a receive frame across the ISA bus. To configure this pin for CS8900A control, the HC1E bit (Register 15, Self- CTL, Bit D) must be clear ...
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... Programmable MAC features include automatic retransmission on collision, and padding of transmitted frames. Figure 8 shows how the MAC engine interfaces to other CS8900A functions. On the host side, it inter- faces to the CS8900A’s internal data/address/con- trol bus. On the network side, it interfaces to the internal Manchester encoder/decoder (ENDEC). ...
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... CRC). When Tx- PadDis is set, the CS8900A will not add pad bits and will transmit frames less that 64 bytes frame is received that is less than 64 bytes (includ- ing CRC), the Runt bit (Register 4, RxEvent, Bit D) will be set indicating the arrival of an illegal frame ...
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... Two primary tasks of the MAC are to avoid network col- lisions, and then recover from them when they oc- cur. In addition, when the CS8900A is using the AUI, the MAC must support the SQE Test function described in section 7.2.4.6 of the Ethernet stan- dard ...
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... Fig- ure 11 diagrams the simple deferral process. 3.9.5.4 Collision Resolution If a collision is detected while the CS8900A is transmitting, the MAC responds in one of three ways depending on whether normal collision (within the first 512 bits of transmission late collision (after the first 512 bits of transmission): 3 ...
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... TestCTL, Bit B). When disabled, the Yes CS8900A only waits the 9.6 µs IPG time before starting transmission. 3.9.5.10 SQE Test If the CS8900A is transmitting on the AUI, the ex- ternal transceiver should generate an SQE Test sig- nal on transmission. The SQE Test MHz signal lasting bit times and starting within 0.6 to ...
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... During this pe- riod, the CS8900A ignores receive carrier activity (see SQE Error in this section for more informa- tion). 3.10 Encoder/Decoder (ENDEC) The CS8900A’s integrated encoder/decoder (EN- DEC) circuit is compliant with the relevant por- tions of section 7 of the Ethernet standard (ISO/IEC 8802-3, 1993). Its primary functions include: Manchester encoding of transmit data ...
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... Auto-Select In Auto-Select mode, the CS8900A automatically selects the 10BASE-T interface and powers down the AUI if valid packets or link pulses are detected by the 10BASE-T receiver. If valid packets and link pulses are not detected, the CS8900A selects DS271PP3 10BASE-T Transceiver Link Pulse RX Squelch ...
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... Link- Loss timer is started. As long as a packet or link pulse is received before the Link-Loss timer finish- es (between 25 and 150 ms), the CS8900A main- tains normal operation receive activity is detected, the CS8900A disables packet transmis- sion to prevent "blind" transmissions onto the net- work (link pulses are still sent while packet transmission is disabled) ...
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... PolarityOK bit is clear. If the PolarityDis bit (Reg- ister 13, LineCTL, Bit C) is clear, the CS8900A au- tomatically corrects a reversal. If the PolarityDis bit is set, the CS8900A does not correct a reversal. The PolarityOK bit and the PolarityDis bit are in- dependent. To detect a reversed pair, the receiver examines re- ceived link pulses and the End-of-Frame (EOF) se- quence of incoming packets ...
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... MAC by asserting the internal Collision signal. 3.13 External Clock Oscillator A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The clock signal should be 20 MHz 0.01% with a duty cycle be- tween 40% and 60% ...
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... Mode is the CS8900A’s default configuration and is used when memory space is not available or when special operations are required (e.g. waking the CS8900A from the Software Suspend State re- quires the host to write to the CS8900A’s assigned I/O space). The user-accessible portion of PacketPage memory is organized into the following six sections: ...
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... Initiate Transmit Registers Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. 40 Crystal LAN™ ISA Ethernet Controller 4.2 PacketPage Memory Map Table 12 shows the CS8900A PacketPage memory ...
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... Write-only Transmit Frame Location Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map (continued) DS271PP3 Description Reserved ...
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... The Product Identification Code Register is located in the first four bytes of the PacketPage (0000h to 0003h). The register contains a unique 32-bit product ID code that identifies the chip as a CS8900A. The host can use this num- ber to determine which software driver to load and to check which features are available. ...
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... DACK7 See Section 3.2 on page 18 and Section 5.4 on page 90. After reset EEPROM is found by the CS8900A, then the register has the following initial state which corre- sponds to setting all DMRQ pins to high-impedance EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base address. The upper three nibbles are reserved. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... XXXX XXXX XXXX 1111 1100 0000 0000 0000 See Section 3.6 on page 25. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... Reset value is: XXXX XXXX XXXX XXXX 46 Crystal LAN™ ISA Ethernet Controller ADD7 to ADD0 Least significant byte of the EEPROM data. Least significant byte of the byte count. CIRRUS LOGIC PRODUCT DATA SHEET CS8900A ELSEL OB1 OB0 Address 0042h Address 0050h DS271PP3 ...
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... Status and Event Registers Status and Event registers report the status of trans- mitted and received frames, as well as information about the configuration of the CS8900A. They are read-only and are designated by even numbers (e.g. Register 2, Register 4, etc.). The Interrupt Status Queue (ISQ special type of Status/Event register ...
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... A. Accept bits indicate which types of frames will be accepted by the CS8900A. (A frame is said to be "accepted" by the CS8900A when the frame data are placed in either on-chip memory host memory by DMA.) Four of these bits have corresponding Interrupt Enable (iE) bits. An Ac- ...
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... RuntiE CRCerroriE RxOKiE If one of the above Interrupt Enable bits is set and the corresponding Accept bit is clear, the CS8900A generates an interrupt when the associated receive DS271PP3 event occurs, but then does not accept the receive frame (the length of the receive frame is set to ze- ro) ...
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... AUIonly BackoffE 10BT HWStan HW SW Sus- dbyE SleepE pend DMA Memo- UseSA DMAex- Burst ryE tend Disable AUIloop ENDEC Backoff loop CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Register Number (Offset (0102h) Promis IAHash 5 cuousA A (0104h) Loss-of- 7 riE CRSiE (0106h) ...
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... CS8900A Crystal LAN™ ISA Ethernet Controller Reserved (register contents undefined) Extra Runt CRC data error Hash Table Index (alternate RxEvent meaning if Hashed = 1 and RxOK = 1) Reserved (register contents undefined) 16coll Number-of-Tx-collisions Reserved (register contents undefined) Rx Dest Reserved (register contents undefined) ...
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... The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C) ...
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... The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set. 54 Crystal LAN™ ISA Ethernet Controller 000100 CRCerror Broadcast 000100 CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Individual Adr Hashed RxOK Hashed = 1 RxOK = 1 DS271PP3 ...
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... See Note 5. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 5.3 on page 87. ...
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... CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt upon detecting the 16th collision. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... TxCFG, Bit 6) is set, there is an interrupt. SQEerror At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error and this bit is set. If SQEerroriE (Register 7, TxCFG, Bit 7) is set, there is an interrupt. ...
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... If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset EEPROM is found by the CS8900A, then the register has the following initial state after reset EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 on page 99 for a description of the transmit bid process.) TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. RxMiss If set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers ...
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... RxMISS actually overflows). The RxMISS counter is cleared when read. 010000 These bits provide an internal address used by the CS8900A to identify this as the Receiver Miss Counter. When reading this register, these bits will be 010000, where the LSB corre- sponds to Bit 0. ...
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... TxCOL actually overflows). The TxCOL counter is cleared when read. 010010 These bits provide an internal address used by the CS8900A to identify this as the Transmit Collision Counter. When reading this register, these bits will be 010010, where the LSB corre- sponds to Bit 0. ...
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... After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... E CRS LineST reports the status of the Ethernet physical interface. 010100 These bits provide an internal address used by the CS8900A to identify this as the Line Status Register. When reading this register, these bits will be 010100, where the LSB corresponds to Bit 0. LinkOK If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the CS8900A has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms ...
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... HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con- trol bit is ignored. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... Status Register. When reading this register, these bits will be 010110, where the LSB corre- sponds to Bit 0. 3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating supply, this bit is clear. INITD If set, the CS8900A initialization, including read-in of the EEPROM, is complete. ...
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... When cleared, the CS8900A will not generate any interrupts. After reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... F E BusST describes the status of the current transmit operation. 011000 These bits provide an internal address used by the CS8900A to identify this as the Bus Status Register. When reading this register, these bits will be 011000, where the LSB corresponds to Bit 0. TxBidErr If set, the host has commanded the CS8900A to transmit a frame that the CS8900A will not send ...
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... This bit must be set when performing loopback tests on the 10BASE-T port. When clear, the CS8900A is configured for standard half-duplex 10BASE-T operation. At reset EEPROM is found by the CS8900A, then the register has the following initial state EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. ...
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... It counts MHz rate from the beginning of transmission on the AUI to when a col- lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read. 011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status Register. When reading this register, these bits will be 011100, where the LSB corresponds to Bit 0. ...
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... When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. ...
Page 72
... The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 3.3 on page 19. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. ...
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... RxEvent register either directly or through the ISQ register. Reading the RxEvent register sig- nals to the CS8900A that the host is finished with the current frame, and wants to start processing the next frame. In this case, the current frame will no longer be accessible to the host ...
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... CS8900A comes out of reset, its default configura- tion is I/O Mode. Once Memory Mode is selected, 74 Crystal LAN™ ISA Ethernet Controller all of the CS8900A’s registers can be accessed di- rectly. In Memory Mode, the CS8900A supports Standard or Ready Bus cycles without introducing additional wait states. ...
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... If Rdy4TxiE (Register B, BufCFG, Bit 8) is set, the host will be interrupt- ed when Rdy4Tx (Register C, BufEvent, Bit 8) becomes set. 3) Once the CS8900A is ready to accept the frame, the host executes repetitive memory-to- memory move instructions (REP MOVS) to memory base + 0A00h to transfer the entire frame from host memory to CS8900A memory ...
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... ISQ, see Section 5.1 on page 79. 4.10.5 PacketPage Pointer Port The PacketPage Pointer Port is written whenever the host wishes to access any of the CS8900A’s in- ternal registers. The first 12 bits (bits 0 through B) provide the internal address of the target register to be accessed during the current operation. The next ...
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... For an I/O Read or Write operation, the AEN pin must be low, and the 16-bit I/O address on the ISA System Address bus (SA0 - SA15) must match the address space of the CS8900A. For a Read, the IOR pin must be low, and for a Write, the IOW pin must be low. ...
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... For a more detailed description of receive, see Section 5.2 on page 79. 4.10.10 Accessing Internal Registers To access any of the CS8900A’s internal registers in I/O Mode, the host must first setup the Pack- etPage Pointer. It does this by writing the Pack- etPage address of the target register to the PacketPage Pointer Port (I/O base + 000Ah) ...
Page 79
... Section 4.3 on page 42. An event triggers an interrupt only when the En- ableIRQ bit of the Bus Control register (bit F of register 17) is set. After the CS8900A has generat interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). INTRQ re- mains low until the null word (0000h) is read from the ISQ, or for 1 ...
Page 80
... BufEvent type? RxMISS TxCOL None of the above Figure 19. Interrupt Status Queue CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Process applicable RxEvent bits: Extradata, Runt, CRCerror, RxOK. Process applicable TxEvent bits: 16coll, Jabber, Out-of-window, TxOK. Process applicable BufEvent bits: RxDest, Rx128, RxMiss, TxUnderrun, Rdy4Tx, RxDMAFrame, SWint ...
Page 81
... The term "transfer" refers to moving data across the ISA bus, to and from the CS8900A. During receive operations, only frame data are transferred from the CS8900A to the host (the preamble and SFD are stripped off by the CS8900A’s MAC engine). The FCS may or may not be transferred, depending on the configuration ...
Page 82
... The RxCFG register (Register 3) and the BusCTL register (Register 17) are used to determine how frames will be transferred to host memory, as de- scribed in Table 22. CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Register 3, RxCFG Operation When set, there is an interrupt if a frame is received with valid length and CRC* ...
Page 83
... When set, DMA buffer size is 64 Kbytes. When clear, DMA buffer size is 16 Kbytes. Table 22. Receive Frame Pre-Processing 5.2.3 Receive Frame Pre-Processing The CS8900A pre-processes all receive frames us- ing a four step process: 1) Destination Address filtering; 2) Early Interrupt Generation; 3) Acceptance filtering; and, 4) Normal Interrupt Generation. ...
Page 84
... RAM, where it awaits processing by the host. Although this re- ceive frame now occupies on-chip memory, the CS8900A does not commit the memory space to it until one of the following two conditions is true: 1) The entire frame has been received and the host ...
Page 85
... CS8900A Crystal LAN™ ISA Ethernet Controller RxDest set. Host may read the DA (first 6 received bytes). Rx128 set and RxDest cleared. Host may read first 128 received bytes. DS271PP3 Receive Frame Yes No DA Filter Discard Frame Passed? Yes 64 bytes Received? No EOF ...
Page 86
... BufEvent reg- ister (Register C), either directly or through the ISQ. When the CS8900A commits buffer space to a par- ticular held receive frame (termed a committed re- ceived frame), no data from subsequent frames can be written to that buffer space until the frame is freed from commitment ...
Page 87
... Ethernet throughput can be achieved by using I/O or memory modes, and by dedicating the CPU to reading this counter, and using the count to read the frame out of the CS8900A at the same time it is being received by the CS8900A from the Ethernet (parallel frame-reception and frame-read-out tasks). ...
Page 88
... Table 25, Broadcast Frames can be ac- cepted as Multicast frames under a very specific set of conditions. 5.3.0.3 Broadcast Frames Frames with DA equal to FFFF FFFF FFFFh are broadcast frames. In addition, the CS8900A can be configured for Promiscuous Mode, in which case it will accept all receive frames, irrespective of DA. IAHashA PromiscuousA MulticastA ...
Page 89
... Crystal LAN™ ISA Ethernet Controller It may become necessary for the host to change the Destination Address (DA) filter criteria without re- setting the CS8900A. This can be done as follows: 1) Clear SerRxON (Register 13, LineCTL, Bit 6) to prevent any additional receive frames while the filter is being changed. ...
Page 90
... NOT (Note 1). Table 25. Contents of RxEvent Upon Various Conditions 5.4 Receive DMA 5.4.1 Overview The CS8900A supports a direct interface to the host DMA controller allowing it to transfer receive frames to host memory via slave DMA. The DMA option applies only to receive frames, and not transmit operation. The CS8900A offers three pos- ...
Page 91
... APPLICATION NOTE result of the PC ar- chitecture, DMA cannot occur across a 128K boundary in memory. Thus, the DMA buffer re- served for the CS8900A must not cross a 128K boundary in host memory if DMA operation is de- sired. Requesting a 64K, rather than a 16K buffer, increases the probability of crossing a 128K bound- ary ...
Page 92
... RxDMAFrame Bit buffer, the The RxDMAFrame bit (Register C, BufEvent, bit 7) is controlled by the CS8900A and is set whenev- er the value in the DMA Frame Count register is non-zero. The host cannot clear RxDMAFrame by reading the BufEvent register (Register C). Table 27 summarizes the criteria used to set and clear RxDMAFrame ...
Page 93
... DMA. The software driver should maintain a pointer (e.g. PDMA_START) that will point to the beginning of a new frame. After the CS8900A is initialized and before any frame is received, pointer PDMA_START points to the beginning of the DMA buffer memory area. The first read of the ...
Page 94
... DMA Figure 25. RxDMA Only Operation 5.5.3 Auto-Switch DMA Operation Whenever a frame begins to be received in Auto- Switch DMA mode, the CS8900A checks to see if there is enough on-chip buffer space to store a max- imum length frame. If there is, the incoming frame is pre-processed and buffered as normal. If there isn’t, the CS8900A’s MAC engine compares the frame’ ...
Page 95
... Frame DMA to transfer partial frames. Also, when a frame Discarded has been committed (see Section 5.2.5 on page 84), the CS8900A will not switch to DMA mode until the committed frame has been transferred com- pletely or skipped. After a complete frame has been moved to host All Frames ...
Page 96
... The host reads a zero value from the DMA Frame Count register (PacketPage base + 0028h). • The CS8900A is not in the process of transfer- ring a frame via DMA. 5.5.6 Auto-Switch DMA Example Figure 27 shows how the CS8900A enters and exits Auto-Switch DMA mode. 5.6 StreamTransfer 5 ...
Page 97
... DMA Frame Count (PacketPage base + 0028h) is zero. Frame 1 received and completely stored in on-chip RAM. Frame 2 received and completely stored in on-chip RAM. At this point, the CS8900A does not have sufficient buffer space for another complete large frame (1518 bytes). Frame 3 starts to be received and passes the DA filter. ...
Page 98
... DA of each packet passes the DA filter. If any of these conditions are not met, the CS8900A exits StreamTransfer by generating RxOK and RxDMA interrupts. The CS8900A then returns to either Memory, I/O, or DMA mode, depending on configuration ...
Page 99
... Ethernet frame into the CS8900A’s buffer memory. The first phase be- gins with the host issuing a Transmit Command. This informs the CS8900A that a frame transmitted and tells the chip when (i.e. after 5, 381, or 1021 bytes have been transferred or after the full frame has been transferred to the CS8900A) and how the frame should be sent (i ...
Page 100
... The host must write the frame’s length to the TxLength register (PacketPage base + 0146h). 3) The host must read the BusST register (Regis- ter 18) The information written to the TxCMD register tells the CS8900A how to transmit the next frame. CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Register 9, TxCMD Operation ...
Page 101
... BusST register (Register 18) and checking the Rdy4TxNOW bit (Bit 8) until the bit is set. When the CS8900A is ready to accept the frame, the host transfers the entire frame from host mem- ory to CS8900A memory using “REP” instruction (REP MOVS starting at memory base + 0A00h in memory mode, and REP OUT to Receive/Transmit Data Port (I/O base + 0000h) in I/O mode) ...
Page 102
... Host Writes Transmit Frame Length to the TxLength Register Host Reads the BusST Register (Register 18) Rdy4 No TxNOW bit = 1? Yes CS8900A Commits Buffer Space to Transmit Frame Host Writes Transmit Frame to CS8900A CS8900A Transmits Frame Exit Transmit Process 3) The host reads the BusST register. This read is performed in memory mode by reading Regis- ter 18, at memory base + 0138h ...
Page 103
... CFG, bit 8) is set, the CS8900A generates a corre- sponding interrupt. 5.7.9 Rdy4TxNOW vs. Rdy4Tx The Rdy4TxNOW bit (Register 18, BusST, bit 8) is used to tell the host that the CS8900A is ready to accept a frame for transmission. This bit is used during the Transmit Request process or after the Transmit Request process to signal the host that space has become available when interrupts are not being used (i ...
Page 104
... Host Writes Transmit Frame Length to the TxLength Register Host Reads the BusST Register (Register 18) Rdy4 Yes TxNOW bit = 1? No Exit WAIT-for-interrupt CS8900A Commits Yes Buffer Space to Transmit Frame Host Writes Transmit Frame to CS8900A CS8900A Transmits Frame Exit Transmit Process Figure 31. Transmit Operation in Interrupt Mode ...
Page 105
... Send without pads and without CRC Notes the TxPadDis bit is clear and InhibitCRC is set and the CS8900A is commanded to send a frame of length less than 60 bytes, the CS8900A pads. 9. The CS8900A will not send a frame with TxLength less than 3 bytes. DS271PP3 this situation is described in the following para- graphs ...
Page 106
... TEST MODES 6.0.1 Loopback & Collision Diagnostic Tests Internal and external Loopback and Collision tests can be used to verify the CS8900A’s functionality when configured for either 10BASE-T or AUI op- eration. 6.0.2 Internal Tests Internal tests allow the major digital functions to be tested, independent of the analog functions. During these tests, the Manchester encoder is connected to the decoder ...
Page 107
... CS8900A enters Boundary Scan test mode and stays in this mode as long as TEST is low; • the CS8900A goes through an internal reset and remains in internal reset as long as TEST is low; • the AEN pin, normally the ISA bus Address Enable, is redefined to become the Boundary Scan shift clock input ...
Page 108
... AEN clock cycles. The first Continuity 97 Cycle can be followed by additional Continuity Cycles by keeping TEST low and continuing to cy- cle AEN. When TEST is driven high, the CS8900A exits Boundary Scan mode and AEN is again used as the ISA-bus Address Enable. Figure 32 shows a complete Boundary Scan Conti- nuity Cycle ...
Page 109
... AEN switches high DS271PP3 Not in Boundary Scan Test Mode TEST switches low (AEN must be low) ENTER BOUNDARY SCAN: CS8900A resets, all digital output pins and bi-directional pins enter High-Z state, and AEN becomes shift clock AEN switches high AEN switches low ...
Page 110
... Crystal LAN™ ISA Ethernet Controller LINKLED LANLED BSTATUS low low low SLEEP copied OUTPUT TEST 34 Clocks COMPLETE CONTINUITY CYCLE 85 Clocks Figure 33. Boundary Scan Timing CIRRUS LOGIC PRODUCT DATA SHEET CS8900A RESET ELCS copied copied out out out INPUT OUTPUTS TEST Clocks 1 clock DS271PP3 ...
Page 111
... V.) Parameter 5.0V Power Supply CS8900A-CQ & -IQ 3.3V Power Supply CS8900A-CQ3 & -IQ3 Operating Ambient Temperature CS8900A-CQ & -CQ3 Operating Ambient Temperature CS8900A-IQ & -IQ3 7.3 DC CHARACTERISTICS Parameter Crystal (when using external clock - square wave) XTAL1 Input Low Voltage XTAL1 Input High Voltage ...
Page 112
... B24 V OH B4w, O24ts OD24, OD10, B24, O24ts B4w ISQ V SQL V AOD V AODU V IDLE V AISQ CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Min Typ Max Unit - - 0 0 0.4 V 0.425 µ ...
Page 113
... CS8900A Crystal LAN™ ISA Ethernet Controller 7.4 SWITCHING CHARACTERISTICS Parameter 16-Bit I/O Read, IOCHRDY Not Used Address, AEN, SBHE active to IOCS16 low Address, AEN, SBHE active to IOR active IOR low to SD valid Address, AEN, SBHE hold after IOR inactive IOR inactive to active ...
Page 114
... MEMR4 t t MEMR6 MEMR2 t t MEMR3 MEMR5 Valid Data 16-Bit Memory Read, IOCHRDY not used Valid Address t MEMR7 t MEMR8 Valid Data t MEMR9 16-Bit Memory Read, with IOCHRDY CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Min Typ Max Unit - - 135 ...
Page 115
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter DMA Read DMACKx active to IOR active AEN active to IOR active IOR active to Data Valid IOR inactive to SD 3-state IOR n-1 high to DMARQx inactive DMACKx, AEN hold after IOR high 16-Bit I/O Write Address, AEN, SBHE valid to IOCS16 low ...
Page 116
... MEMW6 t MEMW7 t TTX1 t TTX2 t TTX3 Valid Address t t MEMW1 MEMW6 MEMW2 MEMW7 MEMW3 t MEMW5 t MEMW4 Valid Data In 16-Bit Memory Write t TTX1 10BASE-T Transmit CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Min Typ Max Unit - - 110 - - ...
Page 117
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter 10BASE-T Receive Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary Carrier Sense Assertion Delay Invalid Preamble Bits after Assertion of Carrier Sense Carrier Sense Deassertion Delay 10BASE-T Link Integrity ...
Page 118
... ARX2 t ARX3 t ARX4 t ARX5 t ACL1 t ACL2 t ACL3 t ACL4 t ACL5 ATX2 AUI Transmit ARX2 t ARX4 AUI Receive t ACL1 t t ACL2 ACL2 AUI Collision CIRRUS LOGIC PRODUCT DATA SHEET CS8900A Min Typ Max Unit - - 0.5 ns 200 - - 8.0 µ ± 240 - ...
Page 119
... CS8900A Crystal LAN™ ISA Ethernet Controller SWITCHING CHARACTERISTICS Parameter External Boot PROM Access Address active to MEMR MEMR active to CSOUT low MEMR inactive to CSOUT high EEPROM EESK Setup time relative to EECS EECS/ELCS_b Setup time wrt EESK EEDataOut Setup time wrt EESK ...
Page 120
... If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor. • The Rt and Rr resistors are ±1% tolerance. • The CS8900A supports 100, 120, and 150 and Rr, for a given cable impedence, are shown below: Cable Impedance ( ) 100 120 150 • ...
Page 121
... CS8900A Crystal LAN™ ISA Ethernet Controller 7.6 AUI WIRING CS8900A Col 7.7 QUARTZ CRYSTAL REQUIREMENTS following specifications) Parameter Parallel Resonant Frequency Resonant Frequency Error ( pF) L Resonant Frequency Change Over Operating Temperature Crystal Capacitance Motional Crystal Capacitance Series Resistance ...
Page 122
... Crystal LAN™ ISA Ethernet Controller INCHES MIN MAX --- 0.063 0.002 0.006 0.007 0.011 0.618 0.642 0.547 0.555 0.618 0.642 0.547 0.555 0.016 0.024 0.018 0.030 0.000° 7.000° CIRRUS LOGIC PRODUCT DATA SHEET CS8900A A A1 MILLIMETERS MIN MAX --- 1.60 0.05 0.15 0.17 0.27 15.70 16.30 13.90 14.10 15.70 16.30 13.90 14.10 0.40 0.60 0.45 0.75 0.00° 7.00° DS271PP3 ...
Page 123
... CS8900A Crystal LAN™ ISA Ethernet Controller 9.0 GLOSSARY OF TERMS 9.1 Acronyms AUI CRC CS CSMA/CD DA EEPROM EOF FCS FDX IA IPG ISA LA LLC MAC MAU MIB RX SA SFD SNMP SOF SQE TDR TX UTP DS271PP3 Attachment Unit Interface Cyclic Redundancy Check Carrier Sense Carrier Sense Multiple Access with Collision Detection ...
Page 124
... Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are active while a packet is being transmitted. 124 Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATA SHEET CS8900A DS271PP3 ...
Page 125
... TxEvent 9.4 Terms Specific to the CS8900A Act-Once bit A control bit that causes the CS8900A to take a certain action once when a logic "1" is written to that bit. To cause the action again, the host must rewrite a "1". Committed Receive Frame A receive frame is said to be "committed" after the frame has been buffered by the CS8900A, and the host has been notified, but the frame has not yet been transferred by the host ...
Page 126
... A feature of the CS8900A used to conserve power. When in Suspend mode, the CS8900A can be awakened only by host command. Transfer The term "transfer" refers to moving frame data across the ISA bus to or from the CS8900A. Transmit Request A Transmit Request is issued by the host to initiate the start of a new packet transmission. A Transmit Request consists of the following three steps in exactly the order shown: 1) The host writes a Transmit Command to the TxCMD register (PacketPage base + 0144h) ...
Page 127
Notes • ...
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