CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 124

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

9.2 Definitions
Cyclic Redundancy Check
Frame Check Sequence
Frame
Individual Address
Inter-Packet Gap
Jabber
Packet
Receive Collision
Signal Quality Error
Slot Time
Transmit Collision
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The method used to compute the 32-bit frame check sequence (FCS).
The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check
(CRC).
An Ethernet string of data bits that includes the Destination Address (DA), Source Address
(SA), optional length field, Logical Link Control data (LLC data), pad bits (if needed) and
Frame Check Sequence (FCS).
The specific Ethernet address assigned to a device attached to the Ethernet media.
Time interval between packets on the Ethernet. Minimum interval is 9.6 ms.
A condition that results when a Ethernet node transmits longer than between 20 ms and 150
ms.
An Ethernet string of data bits that includes the Preamble, Start-of-Frame Delimiter (SFD),
Destination Address (DA), Source Address (SA), optional length field, Logical Link Control
data (LLC data), pad bits (if needed) and Frame Check Sequence (FCS). A packet is a frame
plus the Preamble and SFD.
A receive collision occurs when the CI+/CI- inputs are active while a packet is being received.
Applies only to the AUI.
When transmitting on the AUI, the MAC expects to see a collision signal on the CI+/CI- pair
within 64 bit times after the end of a transmission. If no collision occurs, there is said to be an
"SQE error". Applies only to the AUI.
Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot
Time equals 512 bit times.
A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI-
(AUI) are active while a packet is being transmitted.
CIRRUS LOGIC PRODUCT DATA SHEET
Crystal LAN™ ISA Ethernet Controller
CS8900A
DS271PP3