CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 19

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
DMABurst bit is set, the pin goes low 32 µs after
the start of a DMA transfer.
The DMA pin pairs are arranged on the CS8900A
to facilitate board layout. Crystal recommends the
configuration in Table 2 when connecting these
pins to the ISA bus.
For a description of DMA mode, see Section 5.4 on
page 90.
3.3 Reset and Initialization
3.3.1 Reset
Seven different conditions cause the CS8900A to
reset its internal registers and circuits.
3.3.1.1 External Reset, or ISA Reset
There is a chip-wide reset whenever the RESET pin
is high for at least 400 ns. During a chip-wide reset,
all circuitry and registers in the CS8900A are reset.
3.3.1.2 Power-Up Reset
When power is applied, the CS8900A maintains re-
set until the voltage at the supply pins reaches ap-
proximately 2.5 V. The CS8900A comes out of
reset once Vcc is greater than approximately 2.5 V
and the crystal oscillator has stabilized.
3.3.1.3 Power-Down Reset
If the supply voltage drops below approximately
2.5 V, there is a chip-wide reset. The CS8900A
comes out of reset once the power supply returns to
a level greater than approximately 2.5 V and the
crystal oscillator has stabilized.
CS8900A
Crystal LAN™ ISA Ethernet Controller
DMARQ0 (Pin 15)
DMARQ1 (Pin 13)
DMACK0 (Pin 16)
DMACK1 (Pin 14)
DMARQ2 (Pin 11)
DMACK2 (Pin 12)
CS8900A DMA
Signal (Pin #)
Table 2. DMA Assignments
ISA DMA
DACK5
DACK6
DACK7
Signal
DRQ5
DRQ6
DRQ7
CIRRUS LOGIC PRODUCT DATA SHEET
base + 0024h
PacketPage
0000h
0001h
0002h
3.3.1.4 EEPROM Reset
There is a chip-wide reset if an EEPROM check-
sum error is detected (see Section 3.4 on page 21).
3.3.1.5 Software Initiated Reset
There is a chip-wide reset whenever the RESET bit
(Register 15, SelfCTL, Bit 6) is set.
3.3.1.6 Hardware (HW) Standby or Suspend
The CS8900A goes though a chip-wide reset when-
ever it enters or exits either HW Standby mode or
HW Suspend mode (see Section 3.7 on page 26 for
more information about HW Standby and Sus-
pend).
3.3.1.7 Sof tware (SW) Suspend
Whenever the CS8900A enters SW Suspend mode,
all registers and circuits are reset except for the ISA
I/O Base Address register (located at PacketPage
base + 0020h) and the SelfCTL register (Register
15). Upon exit, there is a chip-wide reset (see
Section 3.7 on page 26 for more information about
SW Suspend).
3.3.2 Allowing Time for Reset Operation
After a reset, the CS8900A goes through a self con-
figuration. This includes calibrating on-chip analog
circuitry, and reading EEPROM for validity and
configuration. Time required for the reset calibra-
tion is typically 10 ms. Software drivers should not
access registers internal to the CS8900A during
this time. When calibration is done, bit INITD in
the Self Status Register (register 16) is set indicat-
ing that initialization is complete, and the SIBUSY
bit in the same register is cleared indicating the EE-
PROM is no longer being read or programmed.
3.3.3 Bus Reset Considerations
The CS8900A reads 3000h from IObase+0Ah after
the reset, until the software writes a non-zero value
at IObase+0Ah. The 3000h value can be used as
part of the CS8900A signature when the system
scans for the CS8900A. See Section 4.10 on
page 76.
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