CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 96

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

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5.5.6 Auto-Switch DMA Example
Figure 27 shows how the CS8900A enters and exits
Auto-Switch DMA mode.
5.6 StreamTransfer
5.6.1 Overview
The CS8900A supports an optional feature,
StreamTransfer, that can reduce the amount of
CPU overhead associated with frame reception.
StreamTransfer works during periods of high re-
ceive activity by grouping multiple receive events
into a single interrupt, thereby reducing the number
of receive interrupts to the host processor. During
periods of peak loading, StreamTransfer will elim-
inate 7 out of every 8 interrupts, cutting interrupt
overhead by up to 87%.
5.6.2 Configuring the CS8900A for
StreamTransfer
StreamTransfer is enabled by setting the StreamE
bit along with either the AutoRxDMAE bit or the
RxDMAonly bit in register Receiver Configuration
(register 3). (StreamTransfer must not be selected
unless either one of AutoRxDMAE or RxDMA-
only is selected.)StreamTransfer only applies to
"good" frames (frames of legal length with valid
CRC). Therefore, the RxOKA bit and the RxOKiE
bit must both be set. Finally, StreamTransfer works
on whole packets and is not compatible with early
interrupts. This requires that the RxDestiE bit and
the Rx128iE bit both be clear.
Table 28 summarizes how to configure the
CS8900A for StreamTransfer.
5.6.3 StreamTransfer Operation
When StreamTransfer is enabled, the CS8900A
will initiate a StreamTransfer cycle whenever two
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The host reads a zero value from the DMA
Frame Count register (PacketPage base +
0028h).
The CS8900A is not in the process of transfer-
ring a frame via DMA.
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or more frames with the following characteristics
are received:
1) pass the Destination Address filter;
2) are of legal length with valid CRC; and,
3) are spaced "back-to-back" (between 9.6 and 52
During a StreamTransfer cycle the CS8900A does
the following:
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5.6.4 Keeping StreamTransfer Mode Active
When the CS8900A initiates a StreamTransfer cy-
cle, it will continue to execute cycles as long as the
following conditions hold true:
Register B, BufCFG
Register 3, RxCFG
Register 5, RxCTL
Register Name
µs apart).
delays the normal RxOK interrupt associated
with the first receive frame;
switches to receive DMA mode;
transfers up to eight receive frames into host
memory via DMA;
updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register (Pack-
etPage base + 0028h);
updates DMA Byte Count register (PacketPage
base + 002Ah);
sets the RxDMAFrame bit (Register C, BufE-
vent, Bit 7); and,
generates an RxDMAFrame interrupt.
Table 28. Stream Transfer Configuration
Crystal LAN™ ISA Ethernet Controller
Bit
or
7
A
F
B
8
9
8
7
AutoRxDMA
RxDMAonly
Bit Name
RxDMAiE
RxDestiE
StreamE
Rx128iE
RxOKiE
RxOKA
or
CS8900A
DS271PP3
Value
or
1
1
1
1
1
1
0
0