CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 101

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
The bits that must be programmed in the TxCMD
register are described in Table 34.
For each individual packet transmission, the host
must issue a complete Transmit Request. Further-
more, the host must write to the TxCMD register
before each packet transmission, even if the con-
tents of the TxCMD register does not change. The
Transmit Request described above may be in either
Memory Space or I/O Space.
5.7.6 Transmit in Poll Mode
In poll mode, Rdy4TxiE bit (Register B, BufCFG,
Bit 8) must be clear (Interrupt Disabled). The trans-
mit operation occurs in the following order and is
shown in Figure 30.
1) The host bids for frame storage by writing the
CS8900A
Crystal LAN™ ISA Ethernet Controller
clear clear
clear set
set clear
set
6
Transmit Command to the TxCMD register
Bit
C
D
8
9
set
7
Table 34. Tx Command Configuration
InhibitCRC When set, the CS8900A
Bit Name
TxPadDis
Tx Start
Onecoll
Force
Register 9, TxCMD
When set, the CS8900A will
Start preamble after 5 bytes
have been transferred to the
CS8900A.
Start preamble after 381
bytes have been trans-
ferred to the CS8900A.
Start preamble after 1021
bytes have been trans-
ferred to the CS8900A.
Start preamble after entire
frame has been transferred
to the CS8900A.
When set, the CS8900A dis-
cards any frame data cur-
rently in the transmit buffer.
When set, the CS8900A will
not attempt to retransmit
any packet after a collision.
does not append the 32-bit
CRC value to the end of any
transmit packet.
not add pad bits to short
frames.
Operation
CIRRUS LOGIC PRODUCT DATA SHEET
2) The host writes the transmit frame length to the
3) The host reads the BusST register. This read is
4) After reading the register, the Rdy4TxNOW bit
When the CS8900A is ready to accept the frame,
the host transfers the entire frame from host mem-
ory to CS8900A memory using “REP” instruction
(REP MOVS starting at memory base + 0A00h in
memory mode, and REP OUT to Receive/Transmit
Data Port (I/O base + 0000h) in I/O mode).
5.7.7 Transmit in Interrupt Mode
In interrupt mode, Rdy4TxiE bit (Register B,
BufCFG, Bit 8) must be set for transmit operation.
Transmit operation occurs in the following order
and is shown in Figure 31.
1) The host bids for frame storage by writing the
2) The host writes the transmit frame length to the
(memory base+ 0144h in memory mode and
I/O base + 0004h in I/O mode).
TxLength register (memory base + 0146h in
memory mode and I/O base + 0006h in I/O
mode). If the transmit length is erroneous, the
command is discarded and the TxBidErr bit
(Register 18, BusST, Bit 7) is set.
performed in memory mode by reading Regis-
ter 18, at memory base + 0138h. In I/O mode,
the host must first set the PacketPage Pointer at
the correct location by writing 0138h to the
PacketPage Pointer Port (I/O base + 000Ah).
The host can then read the BusST register from
the PacketPage Data Port (I/O base + 000Ch).
(Bit 8) is checked. If the bit is set, the frame can
be written. If the bit is clear, the host must con-
tinue reading the BusST register (Register 18)
and checking the Rdy4TxNOW bit (Bit 8) until
the bit is set.
Transmit Command to the TxCMD register
(memory base + 0144h in memory mode and
I/O base + 0004h in I/O mode).
TxLength register (memory base + 0146h in
memory mode and I/O base + 0006h in I/O
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