CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 52

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CS8900-CQ3

Manufacturer Part Number
CS8900-CQ3
Description
Crystal LAN ISA Ethernet Controller
Manufacturer
Cirrus Logic
Datasheet
4.4.5 Register 0: Interrupt Status Queue
(ISQ, Read-only, Address: PacketPage base + 0120h)
The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt
information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s)
in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of
the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register
C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem-
ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See
Section 5.1 on page 79.
RegNum
RegContent
Reset value is: 0000 0000 0000 0000
52
7
F
RegContent
The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ.
The upper ten bits contain the register data contents.
6
E
D
5
CIRRUS LOGIC PRODUCT DATA SHEET
C
4
RegContent
B
3
Crystal LAN™ ISA Ethernet Controller
RegNum
A
2
1
9
CS8900A
DS271PP3
0
8

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