CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 59

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
4.4.12 Register B: Buffer Configuration
(BufCFG, Read/Write, Address: PacketPage base + 010Ah)
Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there is
no interrupt.
001011
SWint-X
RxDMAiE
Rdy4TxiE
TxUnderruniE
RxMissiE
Rx128iE
TxColOvfiE
MissOvfloiE
RxDestiE
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an
EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0000 1011
CS8900A
Crystal LAN™ ISA Ethernet Controller
RxDMAiE
RxDestiE
F
7
SWint-X
figuration Register.
terrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900A acts upon this com-
mand at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1" to this bit.
this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set.
transmission. (See Section 5.7 on page 99 for a description of the transmit bid process.)
frame (called a transmit underrun). When this happens, event bit TXUnderrun (Register C,
BufEvent, Bit 9) is set and the CS8900A makes no further attempts to transmit that frame. If the
host still wants to transmit that particular frame, the host must go through the transmit request
process again.
receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss
bit (Register C, BufEvent, Bit A) is set.
lows a host processor to examine the Destination Address, Source Address, Length, Sequence
Number, and other information before the entire frame is received. This interrupt should not be
used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register
3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.
counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins
(10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.)
200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re-
ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent,
Bit A) is set, and the RxMISS counter (Register 10) is incremented.)
teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in-
coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the
BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from
RxDest to Rx128.
These bits provide an internal address used by the CS8900A to identify this as the Buffer Con-
When set, there is an interrupt requested by the host software. The CS8900A provides the in-
When set, there is an interrupt when a frame has been received and DMA is complete. With
When set, there is an interrupt when the CS8900A is ready to accept a frame from the host for
When set, there is an interrupt if the CS8900A runs out of data before it reaches the end of the
When set, there is an interrupt if one or more received frames is lost due to slow movement of
When set, there is an interrupt after the first 128 bytes of a frame have been received. This al-
If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL
If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from 1FFh to
When set, there is an interrupt when a receive frame passes the Destination Address filter cri-
E
6
Miss OvfloiE
D
5
CIRRUS LOGIC PRODUCT DATA SHEET
TxCol OvfloiE
C
4
Rx128iE
B
3
001011
RxMissiE
A
2
TxUnder runtiE
1
9
Rdy4TxiE
0
8
59