CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 29

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
tion and test. Programmable MAC features include
automatic retransmission on collision, and padding
of transmitted frames.
Figure 8 shows how the MAC engine interfaces to
other CS8900A functions. On the host side, it inter-
faces to the CS8900A’s internal data/address/con-
trol bus. On the network side, it interfaces to the
internal Manchester encoder/decoder (ENDEC).
The primary functions of the MAC are: frame en-
capsulation and decapsulation; error detection and
handling; and, media access management.
3.9.2 Frame Encapsulation and Decapsulation
The CS8900A’s MAC engine automatically as-
sembles transmit packets and disassembles receive
packets. It also determines if transmit and receive
frames are of legal minimum size.
3.9.2.1 Transmission
Once the proper number of bytes have been trans-
ferred to the CS8900A’s memory (either 5, 381,
CS8900A
Crystal LAN™ ISA Ethernet Controller
Internal Bus
CS8900A
Engine
Figure 8. MAC Interface
802.3
Logic
MAC
LED
Direction of Transmission
alternating 1s / 0s
up to 7 bytes
preamble
SFD = Start of Frame Delimiter
DA = Destination Address
SA = Source Address
Encoder/
Decoder
PLL
SFD
&
1 byte
CIRRUS LOGIC PRODUCT DATA SHEET
Figure 9. Ethernet Frame Format
6 bytes
DA
10BASE-T
& AUI
Packet
6 bytes
SA
1021 bytes, or full frame), and providing that ac-
cess to the network is permitted, the MAC automat-
ically transmits the 7-byte preamble (1010101b...),
followed by the Start-of-Frame Delimiter (SFD,
10101011b), and then the serialized frame data. It
then transmits the Frame Check Sequence (FCS).
The data after the SFD and before the FCS (Desti-
nation Address, Source Address, Length, and data
field) is supplied by the host. FCS generation by the
CS8900A may be disabled by setting the Inhibit-
CRC bit (Register 9, TxCMD, bit C).
Figure 9 shows the Ethernet frame format.
3.9.2.2 Reception
The MAC receives the incoming packet as a serial
stream of NRZ data from the Manchester encod-
er/decoder. It begins by checking for the SFD.
Once the SFD is detected, the MAC assumes all
subsequent bits are frame data. It reads the DA and
compares it to the criteria programmed into the ad-
dress filter (see Section 5.3 on page 87 for a de-
scription of Address Filtering). If the DA passes the
address filter, the frame is loaded into the
CS8900A’s memory. If the BufferCRC bit (Regis-
ter 3, RxCFG, bit B) is set, the received FCS is also
loaded into memory. Once the entire packet has
been received, the MAC validates the FCS. If an er-
ror is detected, the CRCerror bit (Register 4, Rx-
Event, Bit C) is set.
3.9.2.3 Enforcing Minimum Frame Size
The MAC provides minimum frame size enforce-
Length Field
max 1518 bytes
LLC = Logical Link Control
FCS = Frame Check Sequence (also
frame length
min 64 bytes
2 bytes
Frame
called Cyclic Redundancy Check, or CRC)
LLC data
Pad
4 bytes
FCS
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