CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 107

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
6.1 Boundary Scan
Boundary Scan test mode provides an easy and ef-
ficient board-level test for verifying that the
CS8900A has been installed properly. Boundary
Scan will check to see if the orientation of the chip
is correct, and if there are any open or short circuits.
Boundary Scan is controlled by the TEST pin.
When TEST is high, the CS8900A is configured
for normal operation. When TEST is low, the fol-
lowing occurs:
•
•
•
•
For Boundary Scan to be enabled, AEN must be
low before TEST is driven low.
A complete Boundary Scan test is made up of two
separate cycles. The first cycle, known as the Out-
put Cycle, tests all digital output pins and all bi-di-
rectional pins. The second cycle, known as the
Input Cycle, tests all digital input pins and all bi-di-
rectional pins.
6.1.1 Output Cycle
During the Output Cycle, the falling edge of AEN
causes each of the 17 digital output pins and each
of the 17 bi-directional pins to be driven low, one
at a time. The cycle begins with LINKLED and ad-
vances in order counterclockwise around the chip
through all 34 pins. This test is referred to as a
"walking 0" test.
CS8900A
Crystal LAN™ ISA Ethernet Controller
the CS8900A enters Boundary Scan test mode
and stays in this mode as long as TEST is low;
the CS8900A goes through an internal reset and
remains in internal reset as long as TEST is
low;
the AEN pin, normally the ISA bus Address
Enable, is redefined to become the Boundary
Scan shift clock input; and
all digital outputs and bi-directional pins are
placed in a high-impedance state (this electri-
cally isolates the CS8900A digital outputs from
the rest of the circuit board).
CIRRUS LOGIC PRODUCT DATA SHEET
The following is a list of output pins and bi-direc-
tional pins that are tested during the Output Cycle:
The output pins not included in this test are:
6.1.2 Input Cycle
During the Input Cycle, the falling edge of AEN
causes the state of each selected pin to be trans-
ferred to EEDataOut (that is, EEDataOut will be
high or low depending on the input level of the se-
lected pin). This cycle begins with SLEEP and ad-
vances clockwise through each of 33 input pins (all
digital input pins except for AEN) and each of the
17 bi-directional pins, one pin at a time.
The following is a list of input pins and bi-direc-
tional pins that are tested during the Input Cycle:
SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74
SD08-SD15 27-24, 21-18
EEDataOut
Pin Name
Pin Name
Pin Name
EEDataIn
CHIPSEL
DMACK2
DMACK1
DMACK0
DMARQ2
DMARQ1
DMARQ0
INTRQ2
MEMW
CSOUT
MEMR
ELCS
EECS
ELCS
EESK
TXD+
DO+
DO-
Pin #
Pin #
Pin #
12
14
16
28
29
2
6
7
11
13
15
17
30
83
84
87
2
3
4
5
Table 40.
Table 38.
Table 39.
SA12 - SA19 50-54, 58-60
SA0 - SA11
REFRESH
Pin Name
MEMCS16
SD0 - SD7 65-68, 71-74
Pin Name
IOCHRDY
Pin Name
BSTATUS
LINKLED
RESET
SLEEP
LANLED
INTRQ1
INTRQ0
IOCS16
INTRQ3
SBHE
XTAL2
IOW
IOR
TXD-
RES
37-48
Pin #
Pin #
Pin #
36
49
61
62
75
77
100
31
32
33
34
35
64
78
99
88
93
98
107