CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 95

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
Figure 26 shows the steps the CS8900A goes
through in determining when to automatically
switch to DMA.
Whenever the CS8900A automatically enters
DMA, at least one complete frame is already stored
in the on-chip buffer. Because frames are trans-
ferred to the host in the same order as received (first
in, first out), the beginning of the received frame
that triggered the switch to DMA is not the first
CS8900A
Crystal LAN™ ISA Ethernet Controller
Figure 26. Conditions for Switching to DMA
Auto-Switch to DMA
Packet Received
Buffer Space
RxDMA only
AutoRxDMA
Available?
Passed the
DA filter?
Bit=1?
Frame
More
Bit=1
Yes
No
No
Yes
No
Yes
Yes
No
in On-chip RAM
Frame Buffered
DMA Disabled
Auto-Switch
Discarded
All Frames
CIRRUS LOGIC PRODUCT DATA SHEET
use DMA
Frame
frame to be transferred. Instead, the oldest noncom-
mitted frame in the on-chip buffer is the first frame
to use DMA. When DMA begins, any pending Rx-
Event reports in the Interrupt Status Queue are dis-
carded because the host cannot process those
events until the corresponding frames have been
completely DMAed.
Auto-Switch DMA works only on entire received
frames. The CS8900A does not use Auto-Switch
DMA to transfer partial frames. Also, when a frame
has been committed (see Section 5.2.5 on page 84),
the CS8900A will not switch to DMA mode until
the committed frame has been transferred com-
pletely or skipped.
After a complete frame has been moved to host
memory, the CS8900A updates the DMA Start-of-
Frame register (PacketPage base + 0126h), the
DMA Frame Count register (PacketPage base +
0128h), and the DMA Byte Count register, then
sets the RxDMAFrame bit (Register C, BufEvent,
bit 7). If RxDMAiE (Register B, BufCFG, bit 7) is
set, a corresponding interrupt occurs.
5.5.4 DMA Channel Speed vs. Missed Frames
When the CS8900A starts DMA, the entire oldest,
noncommitted frame must be placed in host mem-
ory before on-chip buffer space will be freed for the
next incoming frame. If the oldest frame is relative-
ly large, and the next incoming frame also large,
the incoming frame may be missed, depending on
the speed of the DMA channel. If this happens, the
CS8900A will increment the RxMiss counter (Reg-
ister 10) and clear any event reports (RxEvent and
BufEvent) associated with the missed frame.
5.5.5 Exit From DMA
When the CS8900A has activated receive DMA, it
remains in DMA mode until all of the following are
true:
•
The host processes all RxEvent and BufEvent
reports pending in the ISQ.
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