CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 77

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
three bits (C, D, and E) are read-only and will al-
ways read as 011b. Any convenient value may be
written to these bits when writing to the PacketPage
Pointer Port. The last bit (Bit F) indicates whether
or not the PacketPage Pointer should be auto-incre-
mented to the next word location. Figure 18 shows
the structure of the PacketPage Pointer.
4.10.6 PacketPage Data Ports 0 and 1
The PacketPage Data Ports are used to transfer data
to and from any of the CS8900A’s internal regis-
ters. Port 0 is used for 16-bit operations and Port 0
and 1 are used for 32-bit operations (lower-order
word in Port 0).
4.10.7 I/O Mode Operation
For an I/O Read or Write operation, the AEN pin
must be low, and the 16-bit I/O address on the ISA
System Address bus (SA0 - SA15) must match the
address space of the CS8900A. For a Read, the IOR
pin must be low, and for a Write, the IOW pin must
be low.
Note: The ISA Latchable Address Bus (LA17 -
LA23) is not needed for applications that use only
I/O Mode and Receive DMA operation.
4.10.8 Basic I/O Mode Transmit
I/O Mode transmit operations occur in the follow-
ing order (using interrupts):
CS8900A
Crystal LAN™ ISA Ethernet Controller
F E
I/O base + 000Bh
D C
Bit F: 0 = Pointer remains fixed
Figure 18. PacketPage Pointer
B A
1 = Auto-Increments to next word location
9 8
PacketPage Register Address
7 6
I/O base + 000Ah
5 4
CIRRUS LOGIC PRODUCT DATA SHEET
3 2
1 0
1) The host bids for storage of the frame by writ-
2) The host reads the BusST register (Register 18)
3) Once the CS8900A is ready to accept the
For a more detailed description of transmit, see
Section 5.7 on page 99.
4.10.9 Basic I/O Mode Receive
I/O Mode receive operations occur in the following
order (In this example, interrupts are enabled to
signal the presence of a valid receive frame):
1) A frame is received by the CS8900A, triggering
2) The host reads the Interrupt Status Queue Port
3) The host reads the frame data by executing re-
ing the Transmit Command to the TxCMD Port
(I/O base + 0004h) and the transmit frame
length to the TxLength Port (I/O base + 0006h).
to see if the Rdy4TxNOW bit (Bit 8) is set. To
read the BusST register, the host must first set
the PacketPage Pointer at the correct location
by writing 0138h to the PacketPage Pointer
Port (I/O base + 000Ah). It can then read the
BusST register from the PacketPage Data Port
(I/O base + 000Ch). If Rdy4TxNOW is set, the
frame can be written. If clear, the host must
wait for CS8900A buffer memory to become
available. If Rdy4TxiE (Register B, BufCFG,
Bit 8) is set, the host will be interrupted when
Rdy4Tx (Register C, BufEvent, Bit 8) becomes
set. If the TxBidErr bit (Register 18, BusST, Bit
7) is set, the transmit length is not valid.
frame, the host executes repetitive write in-
structions (REP OUT) to the Receive/Transmit
Data Port (I/O base + 0000h) to transfer the en-
tire frame from host memory to CS8900A
memory.
an enabled interrupt.
(I/O base + 0008h) and is informed of the re-
ceive frame.
petitive read instructions (REP IN) from the
Receive/Transmit Data Port (I/O base + 0000h)
to transfer the frame from CS8900A memory to
77