CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 31

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
(Register B, BufCFG, Bit 9) is set, the host is inter-
rupted.
3.9.4 Receive Error Detection and Handling
The following receive errors are reported in the Rx-
Event register (Register 4):
3.9.4.1 CRC Error
If a frame is received with a bad CRC, the CRCer-
ror bit (Register 4, RxEvent, Bit C) is set. If the
CRCerrorA bit (Register 5, RxCTL, Bit C) is set,
the frame will be buffered by CS8900A. If the
CRCerroriE bit (Register 3, RxCFG. Bit C) is set,
the host is interrupted.
3.9.4.2 Runt Frame
If a frame is received that is shorter than 64 bytes,
the Runt bit (Register 4, RxEvent, Bit D) is set. If
the RuntA bit (Register 5, RxCTL, Bit D) is set, the
frame will still be buffered by CS8900A. If the
RuntiE bit (Register 3, RxCFG. Bit D) is set, the
host is interrupted.
3.9.4.3 Extra Data
If a frame is received that is longer than 1518 bytes,
the Extradata bit (Register 4, RxEvent, Bit E) is set.
If the ExtradataA bit (Register 5, RxCTL, Bit E) is
set, the first 1518 bytes of the frame will still be
buffered by CS8900A. If the ExtradataiE bit (Reg-
ister 3, RxCFG. Bit E) is set, the host is interrupted.
3.9.4.4 Dribble Bits and Alignment Error
Under normal operating conditions, the MAC may
detect up to 7 additional bits after the last full byte
of a receive packet. These bits, known as dribble
bits, are ignored. If dribble bits are detected, the
Dribblebit bit (Register 4, RxEvent, Bit 7) is set. If
both the Dribblebits bit and CRCerror bit
(Register 4, RxEvent, Bit C) are set at the same
time, an alignment error has occurred.
3.9.5 Media Access Management
The Ethernet network topology is a single shared
medium with several attached stations. The Ether-
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
net protocol is designed to allow each station equal
access to the network at any given time. Any node
can attempt to gain access to the network by first
completing a deferral process (described below) af-
ter the last network activity, and then transmitting a
packet that will be received by all other stations. If
two nodes transmit simultaneously, a collision oc-
curs and the colliding packets are corrupted. Two
primary tasks of the MAC are to avoid network col-
lisions, and then recover from them when they oc-
cur. In addition, when the CS8900A is using the
AUI, the MAC must support the SQE Test function
described in section 7.2.4.6 of the Ethernet stan-
dard.
3.9.5.1 Collision Avoidance
The MAC continually monitors network traffic by
checking for the presence of carrier activity (carrier
activity is indicated by the assertion of the internal
Carrier Sense signal generated by the ENDEC). If
carrier activity is detected, the network is assumed
busy and the MAC must wait until the current
packet is finished before attempting transmission.
The CS8900A supports two schemes for determin-
ing when to initiate transmission: Two-Part Defer-
ral, and Simple Deferral. Selection of the deferral
scheme is determined by the 2-partDefDis bit
(Register 13, LineCTL, Bit D). If the 2-partDefDis
bit is clear, the MAC uses a two-part deferral pro-
cess defined in section 4.2.3.2.1 of the Ethernet
standard (ISO/IEC 8802-3, 1993). If the 2-partDef-
Dis bit is set, the MAC uses a simplified deferral
scheme. Both schemes are described below:
3.9.5.2 Two-Part Deferral
In the two-part deferral process, the 9.6 µs Inter
Packet Gap (IPG) timer is started whenever the in-
ternal Carrier Sense signal is deasserted. If activity
is detected during the first 6.4 µs of the IPG timer,
the timer is reset and then restarted once the activi-
ty has stopped. If there is no activity during the first
6.4 µs of the IPG timer, the IPG timer is allowed to
time out (even if network activity is detected during
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