CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 75

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
memory space. The other method limits memory
mapping to the first 1 Mbyte of host memory space.
General Memory Mode Operation: Configuring the
CS8900A so that its internal memory can be
mapped anywhere within host Memory space re-
quires the following:
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Limiting Memory Mode to the First 1 Mbyte of
Host Memory Space: Configuring the CS8900A so
that its internal memory can be mapped only within
the first 1 Mbyte of host memory space requires the
following:
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CS8900A
Crystal LAN™ ISA Ethernet Controller
a simple circuit must be added to decode the
Latchable Address bus (LA20 - LA23) and the
BALE signal.
the host must configure the external logic with
the correct address range as follows:
the host must write the memory base address
into the Memory Base Address register (Pack-
etPage base + 002Ch);
the host must set the MemoryE bit (Register 17,
BusCTL, Bit A); and
the host must set the UseSA bit (Register 17,
BusCTL, Bit 9).
the CHIPSEL pin must be tied low;
the ISA-bus SMEMR signal must be connected
to the MEMR pin;
1) Check to see if the INITD bit (Register 16,
2) Check to see if the ELpresent bit (Register
3) Set the ELSEL bit of the EEPROM Com-
4) Configure the external logic serially.
SelfST, bit 7) is set, indicating that initial-
ization is complete.
16, SelfST, bit B) is set. This bit indicates
that external logic for the LA bus decode is
present.
mand Register to activate the ELCS pin for
use with the external decode circuit.
CIRRUS LOGIC PRODUCT DATA SHEET
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4.9.3 Basic Memory Mode Transmit
Memory Mode transmit operations occur in the fol-
lowing order (using interrupts):
1) The host bids for storage of the frame by writ-
2) The host reads the BusST register (Register 18,
3) Once the CS8900A is ready to accept the
For a more detailed description of transmit, see
Section 5.7 on page 99.
4.9.4 Basic Memory Mode Receive
Memory Mode receive operations occur in the fol-
lowing order (interrupts used to signal the presence
of a valid receive frame):
the ISA-bus SMEMW signal must be connect-
ed to the MEMW pin;
the host must write the memory base address
into the Memory Base Address register (Pack-
etPage base + 002Ch);
the host must set the MemoryE bit (Register 17,
BusCTL, Bit A); and
the host must clear the UseSA bit (Register 17,
BusCTL, Bit 9).
ing the Transmit Command to the TxCMD reg-
ister (memory base + 0144h) and the transmit
frame length to the TxLength register (memory
base + 0146h). If the transmit length is errone-
ous, the command is discarded and the Tx-
BidErr bit (Register 18, BusST, Bit 7) is set.
memory base + 0138h). If the Rdy4TxNOW bit
(Bit 8) is set, the frame can be written. If clear,
the host must wait for CS8900A buffer memory
to become available. If Rdy4TxiE (Register B,
BufCFG, Bit 8) is set, the host will be interrupt-
ed when Rdy4Tx (Register C, BufEvent, Bit 8)
becomes set.
frame, the host executes repetitive memory-to-
memory move instructions (REP MOVS) to
memory base + 0A00h to transfer the entire
frame from host memory to CS8900A memory.
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