CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 108

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CS8900-CQ3

Manufacturer Part Number
CS8900-CQ3
Description
Crystal LAN ISA Ethernet Controller
Manufacturer
Cirrus Logic
Datasheet
The input pins not included in this test are:
After the Input Cycle is complete, one more cycle
of AEN returns all digital output pins and bi-direc-
tional pins to a high-impedance state.
108
Pin Name
TEST
AEN
Dl+
Cl+
Dl-
Pin #
63
76
79
80
81
Table 41.
Pin Name
XTAL1
RXD+
RXD-
Cl-
CIRRUS LOGIC PRODUCT DATA SHEET
Pin #
91
82
92
97
6.1.3 Continuity Cycle
The combination of a complete Output Cycle, a
complete Input Cycle, and an additional AEN cycle
is called a Continuity Cycle. Each Continuity Cycle
lasts for 85 AEN clock cycles. The first Continuity
Cycle can be followed by additional Continuity
Cycles by keeping TEST low and continuing to cy-
cle AEN. When TEST is driven high, the CS8900A
exits Boundary Scan mode and AEN is again used
as the ISA-bus Address Enable.
Figure 32 shows a complete Boundary Scan Conti-
nuity Cycle.
Figure 33 shows Boundary Scan timing.
Crystal LAN™ ISA Ethernet Controller
CS8900A
DS271PP3

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