CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 91

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
The size of the circular buffer is determined by the
RxDMAsize bit (Register 17, BusCTL, Bit D).
When RxDMAsize is clear, the buffer size is 16
Kbytes. When RxDMAsize is set, the buffer is 64
Kbytes. It is the host’s task to locate and keep track
of the DMA receive buffer’s base address. The
DMA Start-of-Frame register is the only circuit af-
fected by this bit.
APPLICATION NOTE: As a result of the PC ar-
chitecture, DMA cannot occur across a 128K
boundary in memory. Thus, the DMA buffer re-
served for the CS8900A must not cross a 128K
boundary in host memory if DMA operation is de-
sired. Requesting a 64K, rather than a 16K buffer,
increases the probability of crossing a 128K bound-
ary. After the driver requests a DMA buffer, the
driver must check for a boundary crossing. If the
boundary is crossed, then the driver must disable
DMA functionality.
5.4.4 Receive-DMA-Only Operation
If space is available, an incoming frame is tempo-
rarily stored in on-chip RAM. When the entire
frame has been received, pre-processed, and ac-
cepted, the CS8900A signals the DMA controller
that a frame is to be transferred to host memory by
CS8900A
Crystal LAN™ ISA Ethernet Controller
PacketPage
Address
002Ah
0024h
0026h
0028h
Table 26. Receive DMA Registers
DMA Channel Number: DMA chan-
nel number (0, 1, or 2) that defines the
DMARQ/DMACK pin pair used.
DMA Start of Frame: 16-bit value that
defines the offset from the DMA base
address to the start of the most
recently transferred received frame.
DMA Frame Count: The lower 12 bits
define the number of valid frames
transferred via DMA since the last
read-out of this register. The upper 4
bits are reserved and not applicable.
DMA Byte Count: Defines the num-
ber of bytes that have been transferred
via DMA since the last read-out of this
register.
Register Description
CIRRUS LOGIC PRODUCT DATA SHEET
driving the selected DMA Request pin high. The
DMA controller acknowledges the request by driv-
ing the DMA Acknowledge pin low. The CS8900A
then transfers the contents of the RxStatus register
(PacketPage base + 0400h) and the RxLength reg-
ister (PacketPage base + 0402h) to host memory,
followed by the frame data. If the DMABurst bit
(Register 17, BusCTL, Bit B) is clear, the DMA
Request pin remains high until the entire frame is
transferred. If the DMABurst bit is set, the DMA
Request pin (DMARQ) remains high for approxi-
mately 28 ms then goes low for approximately 1.3
ms to give the CPU and other peripherals access to
the bus.
When the transfer is complete, the CS8900A does
the following:
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•
•
•
•
In addition, if the RxDMAiE bit (Register B,
BufCFG, Bit 7) is set, a corresponding interrupt oc-
curs.
When the host processes DMAed frames, it must
read the DMA Frame Count register.
Whenever a receive frame is missed (lost) due to
insufficient receive buffer space, the RxMISS
counter (Register 10) is incremented. A missed re-
ceive frame causes the counter to increment in ei-
ther DMA or non-DMA modes.
Note that when in DMA mode, reading the contents
of the RxEvent register will return 0000h. Status
updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register (Pack-
etPage base + 0028h);
updates DMA Byte Count register (PacketPage
base + 002Ah);
sets the RxDMAFrame bit (Register C, BufE-
vent, Bit 7); and,
deallocates the buffer space used by the trans-
ferred frame.
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