CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 23

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

DS271PP3
The first word of each group is referred to as the
Group Header. The Group Header indicates the
number of words in the group and the address of the
PacketPage register into which the first data word
in the group is to be loaded. Any remaining words
in the group are stored in successive PacketPage
registers.
3.4.4.1 Group Header
Bits F through C of the Group Header specify the
number of words in each group that are to be trans-
ferred to PacketPage registers (see Figure 4). This
value is two less than the total number of words in
the group, including the Group Header. For exam-
ple, if bits F through C contain 0001, there are three
words in the group (a Group Header and two words
of configuration data).
Bits 8 through 0 of the Group Header specify a 9-
bit PacketPage Address. This address defines the
PacketPage register that will be loaded with the
first word of configuration data from the group.
Bits B though 9 of the Group Header are forced to
0, restricting the destination address range to the
first 512 bytes of PacketPage memory. Figure 4
shows the format of the Group header.
CS8900A
Crystal LAN™ ISA Ethernet Controller
Number of Words
F E
in Group
D C
First Word of a Group of Words
B A
0
Figure 4. Group Header
0
9 8
0
7 6
9-bit PacketPage Address
5 4
CIRRUS LOGIC PRODUCT DATA SHEET
3 2
1 0
3.4.5 Reset Configuration Block Checksum
A checksum is stored in the high byte position of
the word immediately following the last group of
data in the Reset Configuration Block. (The EE-
PROM address of the checksum value can be deter-
mined by dividing the value stored in the Link Byte
by two). The checksum value is the 2’s comple-
ment of the 8-bit sum (any carry out of eighth bit is
ignored) of all the bytes in the Reset Configuration
Block, excluding the checksum byte. This sum in-
cludes the Reset Configuration Block header at ad-
dress 00h. Since the checksum is calculated as the
2’s complement of the sum of all preceding bytes in
the Reset Configuration Block, a total of 0 should
result when the checksum value is added to the sum
of the previous bytes.
3.4.6 EEPROM Example
Table 6 shows an example of a Reset Configuration
Block stored in a C46 EEPROM. Note that little-
endian word ordering is used, i.e., the least signifi-
cant word of a multiword datum is located at the
lowest address.
3.4.7 EEPROM Read-out
If the EEDI pin is asserted high at the end of reset,
the CS8900A reads the first word of EEPROM data
by:
1) Asserting EECS
2) Clocking out a Read-Register-00h command
3) Clocking the data in on EEDI.
If the EEDI pin is low at the end of the reset signal,
the CS8900A does not perform an EEPROM read-
out (uses its default configuration).
3.4.7.1 Determining EEPROM Size
The CS8900A determines the size of the EEPROM
by checking the sense of EEDI on the tenth rising
edge of EESK. If EEDI is low, the EEPROM is a
on EEDO (EESK provides a 1MHz serial clock
signal)
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