CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 60

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

4.4.13 Register C: Buffer Event
(BufEvent, Read-only, Address: PacketPage base + 012Ch)
BufEvent gives the status of the transmit and receive buffers.
001100
SWint
RxDMAFrame
Rdy4Tx
TxUnderrun
RxMiss
Rx128
RxDest
Reset value is:
Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for
RxDMA frame
60
RxDest
7
F
processing all event bits.
0000 0000 0000 1100
SWint
Register. When reading this register, these bits will be 001100, where the LSB corresponds to
Bit 0.
X bit (Register B, BufCFG, Bit 6).
B, BufCFG, Bit 7) is set, there is an interrupt.
ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 on page 99 for a description
of the transmit bid process.)
mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt.
ceive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt.
allow the host the option of preprocessing frame data before the entire frame is received. If
Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt.
as defined in the RxCTL register (Register 5). This bit is useful as an early indication of an in-
coming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE (Register
B, BufCFG, Bit F) is set, there is an interrupt.
These bits provide an internal address used by the CS8900A to identify this as the Buffer Event
If set, there has been a software initiated interrupt. This bit is used in conjunction with the SWint-
If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register
If set, the CS8900A is ready to accept a frame from the host for transmission. If Rdy4TxiE (Reg-
This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans-
If set, one or more receive frames have been lost due to slow movement of data out of the re-
This bit is set after the first 128 bytes of an incoming frame have been received. This bit will
When set, this bit shows that a receive frame has passed the Destination Address Filter criteria
6
E
D
5
CIRRUS LOGIC PRODUCT DATA SHEET
C
4
Rx128
B
3
Crystal LAN™ ISA Ethernet Controller
001100
RxMiss
A
2
TxUnder run
1
9
CS8900A
Rdy4Tx
DS271PP3
0
8