CS8900-CQ3 Cirrus Logic, CS8900-CQ3 Datasheet - Page 90

• Manufacturer Part Number: CS8900-CQ3
• Description: Crystal LAN ISA Ethernet Controller
• Manufacturer: Cirrus Logic

Notes: 6. Broadcast frames are accepted as Multicast frames if and only if all the following conditions are met
5.4 Receive DMA
5.4.1 Overview
The CS8900A supports a direct interface to the host
DMA controller allowing it to transfer receive
frames to host memory via slave DMA. The DMA
option applies only to receive frames, and not
transmit operation. The CS8900A offers three pos-
sible Receive DMA modes:
1) Receive-DMA-only mode: All receive frames
2) Auto-Switch DMA: DMA is used only when
3) StreamTransfer: DMA is used to minimize the
This section provides a description of Receive-
DMA-only mode. Section 5.5 on page 93 describes
Auto-Switch DMA and Section 5.6 on page 96 de-
scribes StreamTransfer.
Received
90
Individual
Address
Multicast
Address
Address
Address
Type of
Frame
Broad-
cast
are transferred via DMA.
needed to help prevent missed frames.
number of interrupts to the host.
7. NOT (Note 1).
Frame?
simultaneously:
a) the Logical Address Filter is programmed as: (MSB) 0000 8000 0000 0000h (LSB). Note that this
LAF value corresponds to a Multicast Addresses of both all 1s and 03-00-00-00-00-01.
b) the Rx Control Register (register 5) is programmed to accept IndividualA, MulticastA, RxOK-only,
and the following address filters were enabled: IAHashA and BroadcastA.
Erred
yes
yes
yes
no
no
no
no
no
no
no
don’t care ExtraData Runt CRC Error Broadcast Individual Adr
don’t care ExtraData Runt CRC Error Broadcast Individual Adr
don’t care ExtraData Runt CRC Error Broadcast Individual Adr
(Note 6)
(Note 7)
Passes
Filter?
Hash
yes
yes
yes
yes
no
no
no
Table 25. Contents of RxEvent Upon Various Conditions
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
ExtraData Runt CRC Error Broadcast Individual Adr
CIRRUS LOGIC PRODUCT DATA SHEET
(actual value X00010)
Hash Table Index
Hash table index
Bits F-A
5.4.2 Configuring the CS8900A for DMA Opera-
tion
The CS8900A interfaces to the host DMA control-
ler through one pair of the DMA request/acknowl-
edge pins (see Section 3.2 on page 18 for a
description of the CS8900A’s DMA interface).
Four 16-bit registers are used for DMA operation.
These are described in Table 26.
Receive-DMA-only mode is enabled by setting the
RxDMAonly bit (Register 3, RxCFG, Bit 9).
Note: If the RxDMAonly bit and the AutoRxD-
MAE bit (Register 3, RxCFG, Bit A) are both set,
then RxDMAonly takes precedence, and the
CS8900A is in DMA mode for all receive frames.
5.4.3 DMA Receive Buffer Size
In receive DMA mode, the CS8900A stores re-
ceived frames (along with their status and length)
in a circular buffer located in host memory space.
Contents of RxEvent
Crystal LAN™ ISA Ethernet Controller
Hashed
Bit 9
1
0
0
1
0
0
1
0
0
0
RxOK
Bit 8
1
1
0
1
1
0
1
1
1
0
CS8900A
DS271PP3
IAHash
Bit 6
1
0
0
0
0
0
0
0
0
0