MCP1631RD-MCC1 Microchip Technology, MCP1631RD-MCC1 Datasheet - Page 183

REFERENCE DESIGN FOR MCP1631HV

MCP1631RD-MCC1

Manufacturer Part Number
MCP1631RD-MCC1
Description
REFERENCE DESIGN FOR MCP1631HV
Manufacturer
Microchip Technology
Type
Battery Managementr

Specifications of MCP1631RD-MCC1

Main Purpose
Power Management, Battery Charger
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
MCP1631HV, PIC16F883
Primary Attributes
1 ~ 2 Cell- Li-Ion, 1 ~ 4 Cell- NiCd/NiMH
Secondary Attributes
Status LEDs
Supported Devices
MCP1631HV, PIC16F883 Device Type
Tool / Board Applications
Power Management-Battery Management
Development Tool Type
Reference Design
Input Voltage
5.5 V to 16 V
Product
Power Management Modules
Mcu Supported Families
MCP1631HV/PIC16F883 Family
Silicon Manufacturer
Microchip
Silicon Core Number
MCP1631HV
Kit Application Type
Reference Design
Application Sub Type
Battery Charger
Kit Contents
Board Only
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MCP1631HV, PIC16F883
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER 13-2:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
WCOL
R/W-0
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Load Mask function
1010 = Reserved
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
2
2
2
2
SSPOV
C mode:
C mode:
C Slave mode:
C Master mode:
R/W-0
is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting
data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register (must be cleared in software).
mode (must be cleared in software).
SSPCON: SSP CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
OSC
OSC
OSC
OSC
PIC16F882/883/884/886/887
R/W-0
/4
/16
/64
/ (4 * (SSPADD+1))
CKP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
2
C conditions were not valid for a transmission to be started
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS41291F-page 181
SSPM0
R/W-0
bit 0

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