MCP1631RD-MCC1 Microchip Technology, MCP1631RD-MCC1 Datasheet - Page 204

• Manufacturer Part Number: MCP1631RD-MCC1
• Description: REFERENCE DESIGN FOR MCP1631HV
• Manufacturer: Microchip Technology
• Type: Battery Managementr

Specifications of MCP1631RD-MCC1

• Main Purpose: Power Management, Battery Charger
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: MCP1631HV, PIC16F883
• Primary Attributes: 1 ~ 2 Cell- Li-Ion, 1 ~ 4 Cell- NiCd/NiMH
• Secondary Attributes: Status LEDs
• Supported Devices: MCP1631HV, PIC16F883 Device Type
• Tool / Board Applications: Power Management-Battery Management
• Development Tool Type: Reference Design
• Input Voltage: 5.5 V to 16 V
• Product: Power Management Modules
• Mcu Supported Families: MCP1631HV/PIC16F883 Family
• Silicon Manufacturer: Microchip
• Silicon Core Number: MCP1631HV
• Kit Application Type: Reference Design
• Application Sub Type: Battery Charger
• Kit Contents: Board Only
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MCP1631HV, PIC16F883
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F882/883/884/886/887
FIGURE 13-18:
13.4.12
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 13-19).
FIGURE 13-19:
DS41291F-page 202
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
CLOCK ARBITRATION
Note: T
SCL
SDA
Falling edge of
9th clock
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
Write to SSPCON2
= one Baud Rate Generator period.
ACK
T
Set PEN
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low
T
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to set up Stop condition
BRG
T
SCL brought high after T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high
P
SCL = 1 for T
after SDA sampled high, P bit (SSPSTAT) is set
13.4.13
While in Sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
13.4.14
A Reset disables the MSSP module and terminates the
current transfer.
T
BRG
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
SLEEP OPERATION
EFFECT OF A RESET
, followed by SDA = 1 for T
T
BRG
SCL = 1, BRG starts counting
clock high interval
© 2009 Microchip Technology Inc.
2
C module can receive
OSC
BRG
*4),