AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 181

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Debug Unit (DBGU)
Overview
1790A–ATARM–11/03
The Debug Unit provides a single entry point from the processor for access to all the debug
capabilities of Atmel’s ARM-based systems.
The Debug Unit features a two-pin UART that can be used for several debug and trace pur-
poses and offers an ideal medium for in-situ programming solutions and debug monitor
communications. Moreover, the association with two peripheral data controller channels per-
mits packet handling for these tasks with processor time reduced to a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by
the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the
status of the DCC read and write registers and generate an interrupt to the ARM processor,
making possible the handling of the DCC under interrupt control.
Chip Identifier registers permit recognition of the device and its revision. These registers
inform as to the sizes and types of the on-chip memories, as well as the set of embedded
peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide
whether to prevent access to the system via the In-circuit Emulator. This permits protection of
the code, stored in ROM.
Important features of the Debug Unit are:
•
•
•
•
•
•
System Peripheral to Facilitate Debug of Atmel’s ARM-based Systems
Composed of Four Functions
–
–
–
–
Two-pin UART
–
–
–
–
–
–
–
Debug Communication Channel Support
–
–
Chip ID Registers
–
ICE Access Prevention
–
–
Two-pin UART
Debug Communication Channel (DCC) Support
Chip ID Registers
ICE Access Prevention
Implemented Features are 100% Compatible with the Standard Atmel USART
Independent Receiver and Transmitter with a Common Programmable Baud Rate
Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two PDC Channels with Connection to Receiver and Transmitter
Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor
Interrupt Generation
Identification of the Device Revision, Sizes of the Embedded Memories, Set of
Peripherals
Enables Software to Prevent System Access Through the ARM Processor’s ICE
Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE
AT91RM3400
181