AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 93

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Peripheral Data Controller (PDC)
Overview
Block Diagram
1790A–ATARM–11/03
The Peripheral Data Controller (PDC) transfers data between on-chip serial peripherals such
as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral
Data Contoller avoids processor intervention and removes the processor interrupt-handling
overhead.This significantly reduces the number of clock cycles required for a data transfer
and, as a result, improves the performance of the microcontroller and makes it more power
efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular periph-
eral. One channel in the pair is dedicated to the receiving channel and one to the transmitting
channel of each UART, USART, SSC and SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains:
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The peripheral triggers PDC transfers using transmit and receive signals. When the pro-
grammed data is transferred, an end of transfer interrupt is generated by the corresponding
peripheral.
Important features of the PDC are:
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Figure 24. Block Diagram
A 32-bit memory pointer register
A 16-bit transfer count register
A 32-bit register for next memory pointer
A 16-bit register for next transfer count
Generates Transfers to/from Peripherals Such as DBGU, USART, SSC, SPI and MCI
Supports Up to Twenty Channels (Product Dependent)
One Master Clock Cycle Needed for a Transfer from Memory to Peripheral
Two Master Clock Cycles Needed for a Transfer from Peripheral to Memory
Peripheral
Control
THR
RHR
Status & Control
PDC Channel 0
PDC Channel 1
Peripheral Data Controller
Control
AT91RM3400
Controller
Memory
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