AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 28

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Status Registers
Exception Types
ARM Instruction
Set Overview
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AT91RM3400
A seventh processing mode, System Mode, does not have any banked registers. It uses the
User Mode registers. System Mode runs tasks that require a privileged processor mode and
allows them to invoke all classes of exceptions.
All other processor states are held in status registers. The current operating processor status
is in the Current Program Status Register (CPSR). The CPSR holds:
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All five exception modes also have a Saved Program Status Register (SPSR) that holds the
CPSR of the task immediately preceding the exception.
The ARM7TDMI
type. The types of exceptions are:
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Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to
the PC. This can be done in two ways:
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The ARM instruction set is divided into:
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ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bit[31:28]).
Table 8 gives the ARM instruction mnemonic list.
four ALU flags (Negative, Zero, Carry, and Overflow)
two interrupt disable bits (one for each type of interrupt)
one bit to indicate ARM or Thumb execution
five bits to encode the current processor mode
fast interrupt (FIQ)
normal interrupt (IRQ)
memory aborts (used to implement memory protection or virtual memory)
attempted execution of an undefined instruction
software interrupts (SWIs)
by using a data-processing instruction with the S-bit set, and the PC as the destination
by using the Load Multiple with Restore CPSR instruction (LDM)
Branch instructions
Data processing instructions
Status register transfer instructions
Load and Store instructions
Coprocessor instructions
Exception-generating instructions
supports five types of exception and a privileged processing mode for each
1790A–ATARM–11/03