AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 5
![KIT DEV FOR AT91RM3400](/photos/9/21/92145/at91rm3400-dk__bottom__sml.jpg)
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 5 of 461
- Download datasheet (6Mb)
Advanced Interrupt
Controller
1790A–ATARM–11/03
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Address Decoder Provides Selection Signals for
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Abort Status Registers
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Misalignment Detector
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Remap Command
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16-area Memory Protection Unit
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Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM
Thirty-two Individually Maskable and Vectored Interrupt Sources
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8-level Priority Controller
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Vectoring
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Protect Mode
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Fast Forcing
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General Interrupt Mask
Handles Requests from the ARM7TDMI and the Peripheral Data Controller
Up to Four Internal 1-Mbyte Memory Areas
One 256-Mbyte Embedded Peripheral Area
Source, Type and All Parameters of the Access Leading to an Abort are
Saved
Facilitates Debug by Detection of Bad Pointers
Alignment Checking of All Data Accesses
Abort Generation in Case of Misalignment
Allows Remapping of an Internal SRAM in Place of the Internal ROM
Allows Handling of Dynamic Interrupt Vectors
Individually Programmable Size Between 1K Bytes and 64M Bytes
Individually Programmable Protection Against Write and/or User Access
Peripheral Protection Against Write and/or User Access
Source 0 is Reserved for the Fast Interrupt Input (FIQ)
Source 1 is Reserved for System Peripherals (e.g., ST, RTC, PMC, DBGU)
Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts
or External Interrupts
Programmable Edge-triggered or Level-sensitive Internal Sources
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
External Sources
Drives the Normal Interrupt of the Processor
Handles Priority of the Interrupt Sources 1 to 31
Higher Priority Interrupts Can Be Served During Service of Lower Priority
Interrupt
Optimizes Interrupt Service Routine Branch and Execution
One 32-bit Vector Register per Interrupt Source
Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
Easy Debugging by Preventing Automatic Operations when Protect ModeIs
Are Enabled
Permits Redirecting any Normal Interrupt Source on the Fast Interrupt of the
Processor
®
Processor
AT91RM3400
5
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