AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 271
![KIT DEV FOR AT91RM3400](/photos/9/21/92145/at91rm3400-dk__bottom__sml.jpg)
AT91RM3400-DK
Manufacturer Part Number
AT91RM3400-DK
Description
KIT DEV FOR AT91RM3400
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91RM3400-DK.pdf
(461 pages)
2.AT91RM3400-DK.pdf
(2 pages)
3.AT91RM3400-DK.pdf
(25 pages)
Specifications of AT91RM3400-DK
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT91RM3400
Data Bus Width
32 bit
Interface Type
RS-232, USB
For Use With/related Products
AT91RM3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 271 of 461
- Download datasheet (6Mb)
Functional Description
Baud Rate
Generator
1790A–ATARM–11/03
The USART is capable of managing several types of serial synchronous or asynchronous
communications.
It supports the following communication modes.
•
•
•
•
•
•
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both
the receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the
Mode Register (US_MR) between:
•
•
•
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD
field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud
Rate Generator does not generate any clock. If CD is programmed at 1, the divider is
bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 4.5 times lower than MCK.
5- to 9-bit full-duplex asynchronous serial communication:
–
–
–
–
–
–
–
–
High-speed 5- to 9-bit full-duplex synchronous serial communication:
–
–
–
–
–
–
–
–
RS485 with driver control signal
ISO7816, T0 or T1 protocols for interfacing with smart cards
–
InfraRed IrDA Modulation and Demodulation
Test modes
–
the Master Clock MCK
a division of the Master Clock, the divider being product dependent, but generally set to 8
the external clock, available on the SCK pin
MSB- or LSB-first
1, 1.5 or 2 stop bits
Parity even, odd, marked, space or none
By-8 or by-16 over-sampling receiver frequency
Optional hardware handshaking
Optional modem signals management
Optional break management
Optional multi-drop serial communication
MSB- or LSB-first
1 or 2 stop bits
Parity even, odd, marked, space or none
By-8 or by-16 over-sampling frequency
Optional Hardware handshaking
Optional Modem signals management
Optional Break management
Optional Multi-Drop serial communication
NACK handling, error counter with repetition and iteration limit
Remote loopback, local loopback, automatic echo
AT91RM3400
271
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