AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 78

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Reset
Management
Recommended
Features of the
Reset
Controller
78
AT91RM3400
Figure 20. NRST Assertion
The system reset functionality is provided via the NRST signal.
The reset signal forces the microcontroller to assume a set of initial conditions:
•
•
With the exception of the program counter and the Current Program Status Register, the pro-
cessor’s registers do not have defined reset states. When the microcontroller’s NRST input is
asserted, the processor immediately stops execution of the current instruction, independent of
the clock.
The system reset circuitry must take two types of reset requests into account:
•
•
Both have the same effect but can have different assertion time requirements regarding the
NRST pin. In fact, the cold reset assertion has to overlap the start-up time of the system. The
user reset request requires a smaller assertion delay time than the cold reset.
The following table gives an overview of the recommended features of a reset controller in
order to obtain an optimal system with the AT91RM3400 device.
Table 25. Reset Controller Function Overview
Feature
Power Supply Monitoring
Reset Active Timeout Period
Manual Reset Command
NRST
Default states (default value) of the user interface are restored.
The processor is required to perform the next instruction fetch from address zero.
Cold reset needed for the power-up sequence
User reset request
Description
Overlaps the transient state of the system during power-up/down
and brownout.
Overlaps the start-up time of the boot-up oscillator by holding the
reset signal during this delay.
Asserts the reset signal from a logic command and holds the reset
signal with a shorter delay than the Reset Active Timeout Period.
RST
1
1790A–ATARM–11/03