AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 403

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Using Endpoints With
Ping-pong Attribute
1790A–ATARM–11/03
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To
be able to guarantee a constant bandwidth, the microcontroller must prepare the next data
payload to be sent while the current one is being sent by the USB device. Thus two banks of
memory are used. While one is available for the microcontroller, the other one is locked by the
USB device.
Figure 166. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data IN
transactions:
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second
5. The microcontroller is notified that the first Bank has been released by the USB device
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB
7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay-
be cleared in the endpoint’s USB_CSRx register.
zero or more byte values in the endpoint’s USB_FDRx register.
FIFO by setting the TXPKTRDY in the endpoint’s USB_CSRx register.
data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the
endpoint’s USB_FDRx register.
when TXCOMP in the endpoint’s USB_CSRx register is set. An interrupt is pending
while TXCOMP is being set.
device that it has prepared the second Bank to be sent rising TXPKTRDY in the end-
point’s USB_CSRx register.
load to be sent
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
.
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
USB Device
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
USB Bus
AT91RM3400
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
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