AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 267

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Universal Synchronous Asynchronous Receiver Transceiver (USART)
Overview
1790A–ATARM–11/03
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely program-
mable (data length, parity, number of stop bits) to support a maximum of standards. The
receiver implements parity error, framing error and overrun error detection. The receiver time-
out enables handling variable-length frames and the transmitter timeguard facilitates commu-
nications with slow remote devices. Multi-drop communications are also supported through
address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 busses, with
ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports.
The hardware handshaking feature enables an out-of-band flow control by automatic manage-
ment of the pins RTS and CTS.
The USART supports the connection to the Peripheral Data Controller, which enables data
transfers to the transmitter and from the receiver. The PDC provides chained buffer manage-
ment without any intervention of the processor.
Important features of the USART are:
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Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
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RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
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IrDA Modulation and Demodulation
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Test Modes
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Supports Connection of Two Peripheral Data Controller Channels (PDC)
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1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous
Mode
Parity Generation and Error Detection
Framing Error Detection, Overrun Error Detection
MSB- or LSB-first
Optional Break Generation and Detection
By 8 or by-16 Over-sampling Receiver Frequency
Optional Hardware Handshaking RTS-CTS
Optional Modem Signal Management DTR-DSR-DCD-RI
Receiver Time-out and Transmitter Timeguard
Optional Multi-Drop Mode with Address Generation and Detection
NACK Handling, Error Counter with Repetition and Iteration Limit
Communication at up to 115.2 Kbps
Remote Loopback, Local Loopback, Automatic Echo
Offer Buffer Transfer without Processor Intervention
AT91RM3400
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