AT91RM3400-DK Atmel, AT91RM3400-DK Datasheet - Page 242

• Manufacturer Part Number: AT91RM3400-DK
• Description: KIT DEV FOR AT91RM3400
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91RM3400-DK

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT91RM3400
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• For Use With/related Products: AT91RM3400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPI Mode Register
Name:
Access Type:
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
*Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration
to be defined by each chip select register.
• DIV32: Clock Selection
0 = The SPI operates at MCK.
1 = The SPI operates at MCK/32.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only.
242
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 15*.
LLB
31
23
15
–
–
7
AT91RM3400
SPI_MR
Read/write
30
22
14
–
–
6
–
29
21
13
–
–
5
–
MODFDIS
28
20
12
–
–
4
DLYBCS
DIV32
27
19
11
–
3
PCSDEC
26
18
10
–
2
PCS
PS
25
17
9
–
1
1790A–ATARM–11/03
MSTR
24
16
–
8
0