C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 127

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

13.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits the reset state.
This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low
until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at 2 MHz. Refer to Section
the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Section
“13.8. Watchdog Timer
location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source
is described in the following sections.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known state
Interrupts and timers are disabled.
RESET SOURCES
(Port
XTAL1
XTAL2
I/O)
CP0+
CP0-
Generator
Reset” on page 129). Once the system clock source is stable, program execution begins at
Internal
Clock
Crossbar
OSC
Comparator0
CNVSTR
(CNVSTR
+
-
“14.
enable)
reset
enable)
OSCILLATORS” on page
(CP0
reset
Clock Select
System
Clock
Figure 13.1. Reset Sources
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
VDD
Core
Handler
Rev. 1.4
EN
WDT
PRE
Supply
Monitor
+
-
Software Reset
System Reset
135
Timeout
Supply
Reset
for information on selecting and configuring
C8051F020/1/2/3
(wired-OR)
Reset
Funnel
/RST
127