C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 187
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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18.3. SMBus Transfer Modes
The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the interface
will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave
Receiver. See Table 18.1 for transfer mode status decoding using the SMB0STA status register. The following mode
descriptions illustrate an interrupt-driven SMBus0 application; SMBus0 may alternatively be operated in polled
mode.
18.3.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START condition and
then transmits the first byte containing the address of the target slave device and the data direction bit. In this case the
data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface transmits one or
more bytes of serial data, waiting for an acknowledge (ACK) from the slave after each byte. To indicate the end of the
serial transfer, SMBus0 generates a STOP condition.
18.3.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus0 interface generates a START
followed by the first data byte containing the address of the target slave and the data direction bit. In this case the data
direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives serial data from
the slave and generates the clock on SCL. After each byte is received, SMBus0 generates an ACK or NACK depend-
ing on the state of the AA bit in register SMB0CN. SMBus0 generates a STOP condition to indicate the end of the
serial transfer.
Interrupt
S
Interrupt
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 18.4. Typical Master Transmitter Sequence
SLA
Figure 18.5. Typical Master Receiver Sequence
W
R
Interrupt
A
Interrupt
A
Data Byte
Data Byte
Rev. 1.4
Interrupt
Interrupt
A
A
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Data Byte
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
C8051F020/1/2/3
Interrupt
N
Interrupt
A
P
P
187
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