C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 188

DEV KIT FOR F020/F021/F022/F023

C8051F020DK

Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F020DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
C8051F020/1/2/3
18.3.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will also ACK if the general call
address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the
data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives the clock on
SCL and transmits one or more bytes of serial data, waiting for an ACK from the master after each byte. SMBus0
exits slave mode after receiving a STOP condition from the master.
18.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if the general call address
(0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direc-
tion bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface receives one or more bytes of
serial data; after each byte is received, the interface transmits an ACK or NACK depending on the state of the AA bit
in SMB0CN. SMBus0 exits Slave Receiver Mode after receiving a STOP condition from the master.
188
S
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
SLA
Figure 18.6. Typical Slave Transmitter Sequence
Figure 18.7. Typical Slave Receiver Sequence
Interrupt
W
R
Interrupt
A
A
Data Byte
Data Byte
Rev. 1.4
Interrupt
Interrupt
A
A
S = START
P = STOP
N = NACK
W = WRITE
SLA = Slave Address
S = START
P = STOP
A = ACK
R = READ
SLA = Slave Address
Data Byte
Data Byte
Interrupt
Interrupt
N
A
Interrupt
Interrupt
P
P

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