C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 176
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 176 of 272
- Download datasheet (2Mb)
C8051F020/1/2/3
176
Bits7-0:
Note:
Bits7-0:
Note:
P3.7
R/W
R/W
Bit7
Bit7
P3.[7:0]: Port3 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.
P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See
FACE AND ON-CHIP XRAM” on page 145
Interface.
P3MDOUT.[7:0]: Port3 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
P3.6
R/W
R/W
Bit6
Bit6
Figure 17.18. P3MDOUT: Port3 Output Mode Register
P3.5
R/W
R/W
Bit5
Bit5
Figure 17.17. P3: Port3 Data Register
P3.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P3.3
Section “16. EXTERNAL DATA MEMORY INTER-
R/W
R/W
Bit3
Bit3
for more information about the External Memory
P3.2
R/W
R/W
Bit2
Bit2
P3.1
R/W
R/W
Bit1
Bit1
(bit addressable)
P3.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
Reset Value
11111111
Reset Value
0xB0
0xA7
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