C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 180
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 180 of 272
- Download datasheet (2Mb)
C8051F020/1/2/3
180
Bits7-0:
Bits7-0:
Note:
P4.7
P5.7
R/W
R/W
Bit7
Bit7
P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
See
page 145
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See
on page 145
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on
P4.6
P5.6
R/W
R/W
Bit6
Bit6
for more information.
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM”
for more information about the External Memory Interface.
P4.5
P5.5
R/W
R/W
Bit5
Bit5
Figure 17.21. P4: Port4 Data Register
Figure 17.22. P5: Port5 Data Register
P4.4
P5.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P4.3
P5.3
R/W
R/W
Bit3
Bit3
P4.2
P5.2
R/W
R/W
Bit2
Bit2
P4.1
P5.1
R/W
R/W
Bit1
Bit1
P4.0
P5.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
11111111
Reset Value
11111111
0x84
0x85
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