C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 269

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT
Register.
Bit7:
Bits6-4:
Bits3-0:
SFLE
Bit7
SFLE: Scratchpad FLASH Memory Access Enable.
When this bit is set, FLASH reads and writes are directed to the 128-byte Scratchpad FLASH sector.
When SFLE is set to logic 1, FLASH accesses out of the address range 0x00-0x7F should not be
attempted. Reads/Writes out of this range will yield unpredictable results.
0:
1:
WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASHDAT
Register per the following values:
000:
001:
010:
(All other values for WRMD3-0 are reserved.)
RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASHDAT Reg-
ister per the following values:
0000:
0001:
0010:
(All other values for RDMD3-0 are reserved.)
WRMD2
Bit6
FLASH access directed to the 64k byte Program/Data FLASH sector.
FLASH access directed to the 128 byte Scratchpad sector.
A FLASHDAT write replaces the data in the FASHDAT register, but is otherwise ignored.
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing
the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x7DFE - 0x7DFF, the entire user space will
be erased (i.e. entire Flash memory except for Reserved area 0x7E00 - 0x7FFF).
A FLASHDAT read provides the data in the FASHDAT register, but is otherwise ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no
operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block) without
initiating an extra read.
Figure 24.3. FLASHCON: JTAG Flash Control Register
WRMD1
Bit5
WRMD0
Bit4
RDMD3
Bit3
Rev. 1.4
RDMD2
Bit2
RDMD1
C8051F020/1/2/3
Bit1
RDMD0
Bit0
00000000
Reset Value
269